參數(shù)資料
型號(hào): MAX9856ETL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/46頁(yè)
文件大?。?/td> 0K
描述: IC AUDIO CODEC 40TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 77 / 91
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 91
電壓 - 電源,模擬: 1.71 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
______________________________________________________________________________________
15
Pin Description
PIN
NAME
FUNCTION
1
LINEIN1
Line 1 Input. AC-couple signal to LINEIN1 with a 1F capacitor.
2
LINEIN2
Line 2 Input. AC-couple signal to LINEIN2 with a 1F capacitor.
3
AUXIN
Auxiliary Input. Input for beep and sound effect signals or can be used for DC measurements.
4
PREG
Positive Internally Regulated Supply (+1.6V ±5%). Bypass to AGND with 1F capacitor.
5
NREG
Negative Internally Regulated Supply (-1.15V ±5%). Bypass to AGND with 1F capacitor.
6
MBIAS
Internal Microphone Bias Regulator Output (1.23V ±5%). Bypass to AGND with a 1F capacitor.
7
REF
Converter Reference (1.23V ±5%). Bypass to AGND with a 1F capacitor.
8
LGNDSNS
Line Output Ground Sense. Feedback path to line-out amplifiers for noise reduction. Connect to the ground
pin of the line output jack. Connect directly to AGND, if ground sense is not required.
9
LOUTL
Left-Channel Line Output. Ground-referenced DirectDrive output.
10
LOUTR
Right-Channel Line Output. Ground-referenced DirectDrive output.
11
HGNDSNS
Headphone Ground Sense. Feedback path to headphone amplifiers for noise reduction. Connect to the
ground pin of the headphone jack. Connect directly to AGND if ground sense is not required.
12
AVDD
Analog Power Supply. Bypass to AGND with 10F and 0.1F capacitors.
13
HPL
Left Headphone DirectDrive Output
14
HPR
Right Headphone DirectDrive Output
15
SVSS
Negative Power-Supply Input. Connect to PVSS and bypass to CPGND with a 4.7F capacitor.
16
PVSS
Internally Generated Negative Supply. Connect to SVSS.
17
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 4.7F capacitor between C1N and C1P.
18
CPGND
Charge-Pump Ground
19
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 4.7F capacitor between C1P and C1N.
20
CPVDD
Charge-Pump Positive Supply. Bypass to CPGND with a 4.7F capacitor.
21
SCL
I2C Serial-Clock Input. Connect a 10k
Ω pullup resistor to DVDD.
22
SDA
I2C Serial-Data Input/Output. Connect a 10k
Ω pullup resistor to DVDD.
23
IRQ
Hardware Interrupt Output.
IRQ can be programmed to pull low when bits in the status register 0x00
change state. Read status register 0x00 to clear
IRQ once set. Repeat faults have no effect on IRQ until it is
cleared by reading the I2C status register 0x00. Connect a 10k
Ω pullup resistor to DVDD for full output
swing.
24
LRCLK_D
Digital Audio Left-Right Clock Input/Output. LRCLK_D is the audio sample rate clock that determines
whether the audio data on SDIN is routed to the left or right channel. LRCLK_D is an input when the
MAX9856 is in slave mode and an output when in master mode. LRCLK_D is also used with SDOUT if
LRCLK_A is configured as a GPIO.
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