參數(shù)資料
型號(hào): MAX9856ETL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 31/46頁(yè)
文件大?。?/td> 0K
描述: IC AUDIO CODEC 40TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 77 / 91
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 91
電壓 - 電源,模擬: 1.71 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
______________________________________________________________________________________
37
Headset Detection
The MAX9856 features headset detection that can detect
the insertion and removal of a jack as well as the load
type. When a jack is detected, an interrupt on
IRQ can be
triggered to alert the microcontroller of the event. Figure 6
shows the typical configuration for jack detection and
Table 14 shows the headset detect control register and
bit description.
Sleep-Mode Jack Detection
When the MAX9856 is in shutdown and the power sup-
ply is available, sleep mode jack detection can be
enabled to detect jack insertion. Sleep mode applies a
2A pullup current to JACKSNS and HPL, which forces
the voltage on JACKSNS and HPL to AVDD when no
load is applied. When a jack is inserted, either JACK-
SNS, HPL, or both are loaded sufficiently to reduce the
output voltage to nearly 0V and clear the JKSNS or
LSNS bits, respectively. The change in the LSNS and
JKSNS bits sets JDET and triggers an interrupt on
IRQ
if IJDET is set. The interrupt signals the microcontroller
that a jack has been inserted, allowing the microcon-
troller to respond as desired.
Powered-On Jack Detection
When the MAX9856 is in normal operation and the
microphone interface is enabled, jack insertion and
removal can be detected through the JACKSNS pin. As
shown in Figure 6, VMIC is pulled up by MICBIAS.
When a microphone is connected, VMIC is assumed to
be between 0V and 95% of VMICBIAS. If the jack is
removed, VMIC increases to VMICBIAS. This event caus-
es JKMIC to be set, alerting the system that the head-
set has been removed. Alternatively, if the jack is
inserted, VMIC decreases to below 95% of VMICBIAS
and JKMIC is cleared, alerting that a jack has been
inserted. The JKMIC bit can be configured to create a
hardware interrupt that alerts the microcontroller of jack
removal and insertion events.
Impedance Detection
The MAX9856 is able to detect the type of load con-
nected by applying a 2mA pullup current to HPL, HPR,
and JACKSNS. To minimize click-and-pop the current
is ramped up and down over a 24ms period. The 2mA
current can be individually applied to HPL, HPR, and
JACKSNS by appropriately configuring the EN bits.
When the 2mA current has finished ramping, HSDETL,
HSDETR, and JSDET are updated to reflect the mea-
sured impedance. EN must be cleared and reset to re-
measure the impedance. Figure 7 and Table 15
illustrate the impedance detection process.
Figure 6. Example Jack Configuration for Jack Detection
I
2mA
SET EN BITS TO 1
SET EN BITS TO 0
tO
tf
tO + 24ms
tf - 24ms
IMPEDANCE
DETECTION
COMPLETE
READ HSDETL,
HSDETR,
JSDET
Figure 7. Current on HPL, HPR, or JACKSNS During Impedance Detection
GND
MIC
HPR
HPL
MICBIAS
JACKSNS
HPR
MICL
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