參數(shù)資料
型號(hào): MAX9856ETL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 13/46頁(yè)
文件大?。?/td> 0K
描述: IC AUDIO CODEC 40TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 77 / 91
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 91
電壓 - 電源,模擬: 1.71 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
20
______________________________________________________________________________________
Status Registers
Status registers 0x00 and 0x01 are read-only registers
that report the status of various device functions. The
status register bits are cleared upon a read operation of
the status register and are set the next time the event
occurs. Table 2 lists the status registers bit location and
description.
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x00
CLD
SLD
ULK
JKMIC
HPOCL
HPOCR
JDET
GPI
0x01
LSNS
JKSNS
HSDETL
HSDETR
JSDET
Table 2. Status Registers Bit Location
BIT
FUNCTION
CLD
Clip Detect Flag. Indicates that a signal has become clipped in the ADC.
SLD
Slew-Level Detect Flag. When volume or gain changes are made, the slewing circuitry smoothly steps through all
intermediate settings. When SLD is set high, all slewing has completed and the volume or gain is at its final value.
ULK
Digital PLL Unlock Flag. Indicates that the digital audio PLL for the DAC or ADC has become unlocked and digital
signal data is not reliable.
JKMIC
Jack Microphone Flag. Indicates JACKSNS has been pulled up to the MICBIAS voltage. The microphone bias
must be enabled for this bit to function properly.
HPOCL/
HPOCR
Headphone Output Left/Right Current Overload Flags. Indicate that the headphone output amplifiers have
exceeded the rated current.
JDET
Headset Configuration Change Flag. Indicates a change in JKMIC, LSNS, or JKSNS.
GPI
GPI State. Indicates the state of LRCLK_A when configured as a general-purpose input.
LSNS
Headphone Sense. LSNS is set when the internal pullup current forces the voltage at HPL to exceed AVDD - 0.4V.
This indicates headphone jack insertion or removal has occurred. HPMODE must be set to 00 and JDETEN set to
1 for this bit to function.
JKSNS
Jack Sense. JKSNS is set when the internal pullup current forces the voltage on JACKSNS to exceed AVDD - 0.4V.
This indicates jack insertion or removal has occurred. JDETEN must be set for this bit to function.
Load Impedance Sense. Indicates the approximate load connected to HPR, HPL, or JACKSNS. These bits are
updated once each time the appropriate EN bits are set high and cause an undefeatable hardware interrupt.
BITS
HEADPHONE OR JACKSNS LOAD
00
200
Ω < load < open
01
50
Ω < load < 200Ω
10
0 < load < 50
Ω
HSDETL,
HSDETR,
JSDET
11
Idle state
Status Register Bit Description
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