參數(shù)資料
型號(hào): MAX9856ETL+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 33/46頁(yè)
文件大小: 0K
描述: IC AUDIO CODEC 40TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類(lèi)型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 77 / 91
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 91
電壓 - 電源,模擬: 1.71 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
______________________________________________________________________________________
39
Power Management and Control
The MAX9856 has comprehensive power management
that allows unused features to be disabled, thereby
saving power. Table 16 shows the power/management
register and a register bit description.
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
0x1C
SHDN
0
DIGEN
LOUTEN
DALEN
DAREN
ADLEN
ADREN
Table 16. Power-Management Register
BITS
FUNCTION
SHDN
Shutdown. Overrides all settings and forces the entire device into a shutdown state.
DIGEN
Digital Core Enable. Set high to use either the DAC or ADC.
LOUTEN
Line Output Enable.
DALEN
Left DAC Enable.
DAREN
Right DAC Enable.
ADLEN
Left ADC Enable.
ADREN
Right ADC Enable.
Power-Management Register Bit Description
SMBus is a trademark of Intel Corp.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START CONDITION
START
CONDITION
tHD, STA
tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tR
tF
Figure 8. 2-Wire Interface Timing Diagram
I2C Serial Interface
The MAX9856 features an I2C/SMBus-compatible,
2-wire serial interface consisting of a serial-data line
(SDA) and a serial-clock line (SCL). SDA and SCL facil-
itate communication between the MAX9856 and the
master at clock rates up to 400kHz. Figure 8 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX9856 by transmitting the
proper slave address followed by the register address
and then the data word. Each transmit sequence is
framed by a START (S) or REPEATED START (Sr) con-
dition and a STOP (P) condition. Each word transmitted
to the MAX9856 is 8 bits long and is followed by an
acknowledge clock pulse. A master reading data from
the MAX9856 transmits the proper slave address
followed by a series of nine SCL pulses. The MAX9856
transmits data on SDA in sync with the master-generated
SCL pulses. The master acknowledges receipt of each
byte of data. Each read sequence is framed by a
START or REPEATED START condition, a not acknowl-
edge, and a STOP condition. SDA operates as both an
input and an open-drain output. A pullup resistor, typi-
cally greater than 500
Ω, is required on SDA. SCL oper-
ates only as an input. A pullup resistor, typically
greater than 500
Ω, is required on SCL if there are mul-
tiple masters on the bus, or if the single master has an
open-drain SCL output. Series resistors in line with
SDA and SCL are optional. Series resistors protect the
digital inputs of the MAX9856 from high voltage spikes
on the bus lines, and minimize crosstalk and under-
shoot of the bus signals.
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