參數(shù)資料
型號: MAX9856ETL+T
廠商: Maxim Integrated Products
文件頁數(shù): 2/46頁
文件大?。?/td> 0K
描述: IC AUDIO CODEC 40TQFN-EP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
類型: 音頻編解碼器
數(shù)據(jù)接口: 串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調變:
S/N 比,標準 ADC / DAC (db): 77 / 91
動態(tài)范圍,標準 ADC / DAC (db): 85 / 91
電壓 - 電源,模擬: 1.71 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.71 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤
供應商設備封裝: 40-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9856
Low-Power Audio CODEC with
DirectDrive Headphone Amplifiers
10
______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SDIN or LRCLK_A/D to BCLK
Rising Setup Time
tSU
BCI = 0 (see the I2C Register Address Map
and Definitions section)
30
ns
SDIN or LRCLK_A/D to BCLK
Rising Hold Time
tHD
BCI = 0 (see the I2C Register Address Map
and Definitions section)
5ns
SDOUT Delay Time
tDLY
BCI = 0 (see the I2C Register Address Map
and Definitions section), CL = 30pF
050
ns
I2C INTERFACE TIMING CHARACTERISTICS
Serial-Clock Frequency
fSCL
0
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD,STA
0.6
s
SCL Pulse Width Low
tLOW
1.3
s
SCL Pulse Width High
tHIGH
0.6
s
Setup Time for a Repeated
START Condition
tSU,STA
0.6
s
Data Hold Time
tHD,DAT
0
900
ns
Data Setup Time
tSU,DAT
100
ns
SDA and SCL Receiving Rise
Time
tr
(Note 10)
20 + 0.1CB
300
ns
SDA and SCL Receiving Fall
Time
tf
(Note 10)
20 + 0.1CB
300
ns
VDVDD = 1.8V (Note 10)
20 + 0.1CB
250
SDA Transmitting Fall Time
tf
VDVDD = 3.6V (Note 10)
20 + 0.05CB
250
ns
Setup Time for STOP Condition
tSU,STO
0.6
s
Bus Capacitance
Cb
400
pF
Pulse Width of Suppressed Spike
tSP
TA = +25°C
0
50
ns
Note 1: All devices are 100% production tested at room temperature. All temperature limits are guaranteed by design.
Note 2: Supply current measurements taken with no applied input signal to line and microphone inputs. A digital zero audio signal
used for all digital serial audio inputs. Speaker and headphone outputs are loaded as stated in the global conditions.
Note 3: DAC performance measured at headphone outputs.
Note 4: Dynamic range measured using the EIAJ method. The input is applied at -60dBFS, fIN = 1kHz. The is THD+N referred to
0dBFS.
Note 5: Signal-to-noise ratio measured using an all-zeros input signal, and is relative to 0dB full scale. The DAC is not muted for the
SNR measurement.
Note 6: Performance measured from line inputs (unless otherwise noted).
Note 7: Microphone amplifiers connected to ADC, microphone inputs AC-grounded.
Note 8: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock
rate. (VDVDD = 1.8V, unless otherwise noted).
Note 9: To enable the line input, make sure the desired input is selected by either the audio output mixer or the ADC input mixer.
Note 10: CB is in pF.
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VDVDDS2 = 1.8V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
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