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參數(shù)資料
| 型號： | M470T2953CZ3-CE7 |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.4 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | M470T2953CZ3-CE7 |
Rev. 1.6 March 2007
SODIMM
DDR2 SDRAM
Page 2 of 20
Table of Contents
1.0 DDR2 Unbuffered SODIMM Ordering Information .................................................................... 4
2.0 Features ........................................................................................................................................ 4
3.0 Address Configuration ................................................................................................................ 4
4.0 Pin Configurations (Front side/Back side) ................................................................................ 5
5.0 Pin Description ............................................................................................................................. 5
6.0 Input/Output Functional Description .......................................................................................... 6
7.0 Functional Block Diagram : ......................................................................................................... 7
7.1 512MB, 64Mx64 Module - M470T6554CZ3/M470T6554CZ0
.................................................................. 7
7.2 256MB, 32Mx64 Module - M470T3354CZ3/M470T3354CZ0
.................................................................. 8
7.3 1GB, 128Mx64 Module - M470T2953CZ3/M470T2953CZ0
.................................................................... 9
8.0 Absolute Maximum DC Ratings ................................................................................................10
9.0 AC & DC Operating Conditions ................................................................................................ 10
9.1 Recommended DC Operating Conditions (SSTL - 1.8)
..................................................................... 10
9.2 Operating Temperature Condition
................................................................................................ 11
9.3 Input DC Logic Level
................................................................................................................... 11
9.4 Input AC Logic Level
................................................................................................................... 11
9.5 AC Input Test Conditions
............................................................................................................ 11
10.0 IDD Specification Parameters Definition ............................................................................... 12
11.0 Operating Current Table .......................................................................................................... 13
11.1 M470T6554CZ3/M470T6554CZ0 : 64Mx64 512MB Module
.............................................................. 13
11.2 M470T3354CZ3/M470T3354CZ0 : 32Mx64 256MB Module
.............................................................. 13
11.3 M470T2953CZ3/M470T2953CZ0 : 128Mx64 1GB Module
............................................................... 14
12.0 Input/Output Capacitance ....................................................................................................... 15
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 ..................................... 15
13.1 Refresh Parameters by Device Density
...................................................................................... 15
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
............................................ 15
13.3 Timing Parameters by Speed Grade
.......................................................................................... 16
14.0 Physical Dimensions : ............................................................................................................. 18
14.1 32Mbx16 based 64Mx64 Module(2 Rank)
.................................................................................... 18
14.2 32Mbx16 based 32Mx64 Module(1 Rank)
..................................................................................... 19
14.3 64Mbx8 based 128Mx64 Module(2 Ranks)
.................................................................................. 20
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M470T2953CZ3-CLCC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T2953CZ3-CLD5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T2953CZ3-CLE6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T2953CZ3-CLE7 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 512Mb C-die 64bit Non-ECC |
| M470T2953EZ3CE600 | 制造商:Samsung Semiconductor 功能描述: |
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