參數(shù)資料
型號(hào)： M37902FCCHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 74/143頁(yè)
文件大?。?/td> 1463K
代理商： M37902FCCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
74
Table 13. Selection methods of CTS/RTS function
CTS
i
/RTS
i
separate select bit
0
1
Functions
CTS
0
RTS
0
RTS
0
P8
0
Pin P8
1
/CTS
0
/CLK
0
P8
1
or CLK
0
P8
1
or CLK
0
CTS
0
(Notes 2 and 3)
P8
1
or CLK
0
Pin P8
4
/CTS
1
/RTS
1
CTS
1
RTS
1
RTS
1
P8
4
Pin P8
5
/CTS
1
/CLK
1
P8
5
or CLK
1
P8
5
or CLK
1
CTS
1
(Notes 2 and 3)
P8
5
or CLK
1
Notes 1:
When using the CTS
0
/RTS
0
pin, be sure to clear the D-A
2
output enable bit (bit 2 at address 96
16
) to
“
0
”
.
2:
When using the CTS function, be sure to clear the corresponding bit of the port P8 direction register to
“
0
”
.
3:
When CTSi and RTSi has been separated, the CLKi pin cannot be used. Therefore, in the clock synchronous serial communication, CTSi and RTSi
cannot be separated. Also, when CTSi and RTSi are separated in UART mode, be sure to select an internal clock.
CTS/RTS
function select bit
CTS/RTS
enable bit
0
1
0
1
Pin P8
0
/CTS
0
/RTS
0
(Note 1)
: It may be
“
0
”
or
“
1
”
.
Fig. 76 Bit configuration of serial I/O pin control register
CTS
0
/RTS
0
separate select bit
0 : CTS
0
/RTS
0
are used together.
1 : CTS
0
/RTS
0
are separated.
CTS
1
/RTS
1
separate select bit
0 : CTS
1
/RTS
1
are used together.
1 : CTS
1
/RTS
1
are separated.
TxD
0
/P8
3
switch bit
0 : Functions as TxD
0.
1 : Functions as P8
3.
TxD
1
/P8
7
switch bit
0 : Functions as TxD
1.
1 : Functions as P8
7.
7 6 5 4 3 2 1 0
Serial I/O pin control register
Address
AC
16
At reset
X0
16
Receive
Receive is enabled when bit 2 (REi flag) of UARTi transmit/receive
control register 1 is set to
“
1.
”
As shown in Figure 75, the frequency
divider circuit (1/16) at the receiving side begin to work when a start
bit arrives and the data is received.
If RTSi output is selected by setting bit 2 of UARTi transmit/receive
control register 0 to
“
1
”
, the RTSi output is
“
“
0
”
. When the REi flag changes to
“
1
”
, the RTSi output goes
“
L
”
to
inform the receiver that reception has become enabled. When the
receive operation starts, the RTSi output automatically becomes
“
H
”
.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 66. At this
point, the contents of the receive register is transferred to the receive
buffer register and bit 3 (Rli flag) of UARTi transmit/receive control
register 1 is set to
“
1.
”
In other words, the RIi flag indicates that the
receive buffer register contains data when it is set to
“
1.
”
At this time,
when the low-order byte of the UARTk receive buffer register is read
out, RTSi output goes back to
“
L
”
to indicate that the register is ready
to receive the next data.
Bit 4 (OERi flag) of UARTi transmit/receive control register 1 is set to
“
1
”
when the next data is transferred from the receive register to the
receive buffer register while the RIi flag is
“
1
”
, in other words, when
an overrun error occurs. If the OERi flag is
“
1
”
, it indicates that the
next data has been transferred to the receive buffer register before
the contents of the receive buffer register has been read.
Bit 5 (FERi flag) is set to
“
1
”
when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set to
“
1
”
when a parity error occurs.
Bit 7 (SUMi flag) is set to
“
1
”
when either the OERi flag, FERi flag, or
the PERi flag is set to
“
1.
”
Therefore, the SUMi flag can be used to
determine whether there is an error.
The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag is
performed while transferring the contents of the receive register to
the receive buffer register.
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