參數(shù)資料
型號： M37902FCCHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機
文件頁數(shù)： 33/143頁
文件大?。?/td> 1463K
代理商： M37902FCCHP
33
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Microprocessor mode
V
CC
level voltage is applied
10
SFR area
Internal RAM area
External memory area
External memory area
Low-order address (A
0
to A
7
) is output.
Middle-order address (A
8
to A
15
) is
output.
I/O port pins P11
0
to P11
7
(Note 3)
High-order address (A
16
to A
23
) is out-
put.
I/O port pins P0
0
to P0
7
(Note 3)
Low-order data (D
0
to D
7
, data at
even address) is input/output.
Low-order data (D
0
to D
7
, data at
even/odd address) is input/output.
Low-order address (LA
0
to LA
7
) is out-
put. Low-order data (D
0
to D
7
, data at
even/odd address) is input/output
(Note 4)
.
High-order data (D
8
to D
15
, data at
odd address) is input/output.
I/O port pins P2
0
to P2
7
(Note 5)
Ready signal RDY is input.
I/O port pin P3
0
(Note 6)
Read signal RD is output
Write signal BLW (write to even ad-
dress) is output.
Write signal BLW (write to even/odd
address) is output.
Write signal BHW (write to odd ad-
dress) is output.
I/O port pin P3
3
(Note 5)
Memory expansion mode
V
SS
level voltage is applied
01
SFR area
Internal RAM area
Internal ROM area
External memory area
Low-order address (A
0
to A
7
) is output.
Middle-order address (A
8
to A
15
) is
output.
I/O port pins P11
0
to P11
7
(Note 3)
High-order address (A
16
to A
23
) is out-
put.
I/O port pins P0
0
to P0
7
(Note 3)
Low-order data (D
0
to D
7
, data at
even address) is input/output.
Low-order data (D
0
to D
7
, data at
even/odd address) is input/output.
Low-order address (LA
0
to LA
7
) is out-
put. Low-order data (D
0
to D
7
, data at
even/odd address) is input/output
(Note 4)
.
High-order data (D
8
to D
15
, data at
odd address) is input/output.
I/O port pins P2
0
to P2
7
(Note 5)
I/O port pin P3
0
Ready signal RDY is input
(Note 6).
Read signal RD is output.
Write signal BLW (write to even ad-
dress) is output.
Write signal BLW (write to even/odd
address) is output.
Write signal BHW (write to odd ad-
dress) is output.
I/O port pin P3
3
(Note 5)
Table 5. Relationship between processor modes, memory area, and port function (1)
Single-chip mode
V
SS
level voltage is applied
Pin MD0
Processor mode
bits
(Note 2)
SFR area
Internal RAM area
Internal ROM area
Other area
Mode
(Note 1)
00
SFR area
Internal RAM area
Internal ROM area
(Do not access.)
I/O port pins P10
0
to P10
7
I/O port pins P11
0
to P11
7
I/O port pins P0
0
to P0
7
I/O port pins P1
0
to P1
7
I/O port pins P2
0
to P2
7
I/O port pin P3
0
I/O port pin P3
1
I/O port pin P3
2
I/O port pin P3
3
M
Port pins P10
0
to P10
7
Port pins P11
0
to P11
7
Port pins P0
0
to P0
7
Port pins
P1
0
to P1
7
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 8 bits
Port pins
P2
0
to P2
7
Port pin P3
0
Port pin P3
1
External data bus
width = 16 bits
External data bus
width = 8 bits
External data bus
width = 16 bits
External data bus
width = 8 bits
Port pin
P3
2
Port pin
P3
3
External data bus
width = 16 bits
相關(guān)PDF資料
PDF描述
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