參數(shù)資料
型號(hào)： M37902FCCHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 46/143頁(yè)
文件大?。?/td> 1463K
代理商： M37902FCCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
46
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INTERRUPTS
Table 8 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also handled as a type of interrupt in this
section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, NMI, and
address matching detection all have interrupt control registers. Table
9 shows the addresses of the interrupt control registers and Figure
35 shows the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits other than watchdog timer and NMI can be cleared by software.
An NMI interrupt request is a non-maskable interrupt by an external
input and is accepted at the falling edge of an input to pin NMI. Also,
pin NMI has the pullup function. For more details, refer to the section
on input/output pins.
An INT
i
(i = 0 to 4) interrupt request is generated by an external in-
put.
INT
0
to INT
2
are external interrupts; whether to cause an interrupt at
the input level (level sense) or at the edge (edge sense) can be se-
lected with the level/edge select bit. Furthermore, the polarity of the
interrupt input can be selected with the polarity select bit.
For INT
3
and INT
4,
the interrupt signal’s polarity can be change by
the polarity select bit. (This is valid only in the edge sense.)
By pins INT
2
to INT
4
select bits (bits 4 to 6 at address 94
16
; see Fig-
ure 40.), pin position of INT
2
to INT
4
can be changed.
When using the following pins as external interrupt input pins, clear
the direction registers of the corresponding multiplexed ports to “0”:
pins P6
2
/INT
0
, P6
3
/INT
1
, P6
4
(P7
7
)/INT
2
, P8
0
(P7
4
)/INT
3
, and
P8
4
(P7
5
)/INT
4
.
Furthermore, the INT
3
interrupt can function as the key input inter-
rupt. For details, refer to the section on the key input interrupt.
When the external interrupt input read register (address 95
16
) is read
out, the status of pins INT
0
to INT
4
and NMI can directly be read.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupt requests are caused
simultaneously is partially fixed by hardware, but, it can also be ad-
justed by software as shown in Figure 36.
The hardware priority is fixed as the following:
reset > NMI > watchdog timer > other interrupts
Interrupts
Address matching detection interrupt
INT
4
external interrupt
INT
3
external interrupt
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
external interrupt
INT
1
external interrupt
INT
0
external interrupt
NMI external interrupt
Watchdog timer
DBC (Do not select.)
Break instruction (Do not select.)
Zero divide
Reset
Table 8. Interrupt sources and interrupt vector addresses
Vector addresses
00FFCA
16
00FFCB
16
00FFD0
16
00FFD1
16
00FFD2
16
00FFD3
16
00FFD4
16
00FFD6
16
00FFD8
16
00FFDA
16
00FFDC
16
00FFDE
16
00FFE0
16
00FFE2
16
00FFE4
16
00FFE6
16
00FFE8
16
00FFEA
16
00FFEC
16
00FFEE
16
00FFF0
16
00FFF2
16
00FFF4
16
00FFF6
16
00FFF8
16
00FFFA
16
00FFFC
16
00FFFE
16
00FFD5
16
00FFD7
16
00FFD9
16
00FFDB
16
00FFDD
16
00FFDF
16
00FFE1
16
00FFE3
16
00FFE5
16
00FFE7
16
00FFE9
16
00FFEB
16
00FFED
16
00FFEF
16
00FFF1
16
00FFF3
16
00FFF5
16
00FFF7
16
00FFF9
16
00FFFB
16
00FFFD
16
00FFFF
16
Fig. 34 Bit configuration of external interrupt input read register
7
6
5
4
3
2
1
0
Note:
When the key input interrupt select bit (bit 0 at address 94
16
) =
“
1
”
,
the status of pin INT
3
cannot be read out.
INT
0
read bit
INT
1
read bit
INT
2
read bit
INT
3
read bit
(Note)
INT
4
read bit
NMI read bit
Undefined at read.
External interrupt input read register
Address
95
16
相關(guān)PDF資料
PDF描述
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