參數(shù)資料
型號(hào): M37902FCCHP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 30/143頁(yè)
文件大小: 1463K
代理商: M37902FCCHP
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M37902FCCHP, M37902FGCHP, M37902FJCHP
MITSUBISHI MICROCOMPUTERS
30
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
G
Area multiplication
When area CS
2
s external data bus width = 8 bits with the multi-
plexed bus select bit of the CS
2
control register H (bit 5 at address
85
16
) =
1
, the external bus type can be changed to the multiplexed
bus type only at access to area CS
2
. In this case, the low-order 8 bits
of an address (LA
0
to LA
7)
are output, and the low-order 8 bits of
data (D
0
to D
7)
are input/output with the time-sharing method, re-
spectively.
Figure 22 shows a waveform example of area multiplication for each
bus cycle. Do not select the area multiplication function for a bus
cycle not shown in Figure 22.
Fig. 22 Waveform example of area multiplication for each bus cycle
D
0
to D
7
1 1
1 0
1 1
Multiplexed bus select bit = 1
Bus cycle
select bit 0
RD,
BLW
1 bus cycle = 6
φ
φ
1
CS
i
ALE
3
φ
3
φ
RD,
BLW
1 bus cycle = 7
φ
φ
1
CS
i
ALE
4
φ
3
φ
D
0
to D
7
D
0
to D
7
D
0
to D
7
External address bus
Address
External address bus
Address
Bus cycle 2
φ
+ 2
φ
Bus cycle 3
φ
+ 3
φ
Bus cycle 3
φ
+ 4
φ
RD,
BLW
φ
1
At write, LA
0
/D
0
to LA
7
/D
7
CS
i
ALE
D
0
to D
7
1 bus cycle = 4
φ
D
0
to D
7
External address bus
Address
0
1
1
Area CS
2
bus
cycle select
bit 0
At read, LA
0
/D
0
to LA
7
/D
7
At write, LA
0
/D
0
to LA
7
/D
7
At read, LA
0
/D
0
to LA
7
/D
7
At write, LA
0
/D
0
to LA
7
/D
7
At read, LA
0
/D
0
to LA
7
/D
7
LA
0
to LA
7
LA
0
to LA
7
LA
0
to LA
7
LA
0
to LA
7
LA
0
to LA
7
LA
0
to LA
7
Notes 1:
The number of bus cycles is determined by the following bits:
Area CS
2
bus cycle select bit 0 (bits 0 and 1 at address 84
16
)
Area CS
2
bus cycle select bit 1 (bit 3 at address 85
16
)
Area multiplication is specified by the multiplexed bus select bit (bit 5 at address 85
16
).
2:
Do not select the area multiplication function for a bus cycle not shown in Figure 22.
2
φ
2
φ
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