參數(shù)資料
型號: M37902F8CHP
廠商: Mitsubishi Electric Corporation
英文描述: DIODE SCHOTTKY DUAL COMMON-ANODE 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-23 3K/REEL
中文描述: 單片16位CMOS微機
文件頁數(shù): 78/143頁
文件大?。?/td> 1463K
代理商: M37902F8CHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
78
Fig. 79 Bit configuration of A-D control register 1
0
7
6
5
4
3
2
1
0
A-D sweep pin select bits
(Note 1)
(Valid in the single sweep mode and repeat sweep mode.)
0 0 : AN
0
, AN
1
0 1 : AN
0
AN
3
1 0 : AN
0
AN
5
1 1 : AN
0
AN
7
Must be
0
.
Resolution select bit
0: 8-bit mode
1: 10-bit mode
A-D conversion frequency (
φ
AD
) select bit 1
External trigger polarity select bit
(Valid when external trigger is selected.)
0: Falling edge of input signal to the AD
TRG
pin
1: Rising edge of input signal to the AD
TRG
pin
V
REF
connection select bit
(Note 6)
0 : V
REF
is connected.
1 : V
REF
is not connected.
0
at read.
(2 pins)
(4 pins)
(6 pins)
(Notes 2, 3)
(8 pins)
(Notes 2 to 5)
A-D control register 1
Address
1F
16
A-D conversion frequency (
φ
AD
) select bit
Bit 1
0
0
0
1
1
1
0
1
Bit 0
φ
AD
f
2
/4
f
2
/2
f
2
f
1
(Selectable only in 8-bit mode)
Notes 1:
Ignored in the one-shot and repeat modes. (Each of these bits may be
0
or
1
.)
2:
When using the AN
4
pin, be sure to clear the INT
3
pin select bit (bit 5 at address 94
16
) to
0
.
3:
When using the AN
5
pin, be sure to clear the INT
4
pin select bit (bit 6 at address 94
16
) to
0
.
4:
When using the AN
6
pin, be sure to clear the D-A
0
output enable bit (bit 0 at address 96
16
) to
0
(output disabled).
5:
When using the AN
7
pin, be sure to clear both of the INT
2
pin select bit (bit 4 at address 94
16
)
and the D-A
1
output enable bit (bit 1 at address 96
16
) to
0
. When an external trigger is selected,
the AN
7
pin cannot be used as an analog input pin.
6:
Once this bit is cleared from
1
to
0
, it is necessary to wait for 1
μ
s or more before the A-D or
D-A conversion starts.
7:
Rewriting to each bit of the A-D control register 1 must be performed while A-D conversion is stopped.
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