- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄370849 > M37902F8CHP (Mitsubishi Electric Corporation) DIODE SCHOTTKY DUAL COMMON-ANODE 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-23 3K/REEL PDF資料下載
參數(shù)資料
| 型號(hào)： | M37902F8CHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | DIODE SCHOTTKY DUAL COMMON-ANODE 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-23 3K/REEL |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 107/143頁(yè) |
| 文件大?。?/td> | 1463K |
| 代理商： | M37902F8CHP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)當(dāng)前第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)
107
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Function overview (CPU reprogramming mode)
The CPU reprogramming mode is available in the single-chip mode,
memory expansion mode, and boot mode to reprogram the user
ROM area only.
In the CPU reprogramming mode, the CPU erases, programs, and
reads the internal flash memory by writing software commands. Note
that the user-original reprogramming control software must be trans-
ferred to the internal RAM in advance to be executed.
The CPU reprogramming mode becomes active when
“
1
”
is written
into the flash memory control register
’
s bit 1 (the CPU reprogram-
ming mode select bit) shown in Figure 114, and software commands
become acceptable.
In the CPU reprogramming mode, software commands and data are
all written to and read from even addresses (Note that address A
0
in
byte addresses =
“
0
”
.) 16 bits at a time. Therefore, a software com-
mand consisting of 8 bits must be written to an even address; there-
fore, any command written to an odd address will be invalid. Since
the write data at the 2nd cycle of a programming command consists
of 16 bits, this data must be written to even and odd addresses.
The write state machine (WSM) in the flash memory controls the
erase and programming operations. What the status of the WSM
operation is and whether the programming or erase operation has
been completed normally or terminated by an error can be examined
by reading the status register.
Figure 114 shows the bit configuration of the flash memory control
register.
Bit 0 (the RY/BY status bit) is a read-only bit for indicating the WSM
operation. This bit goes to
“
0
”
(BUSY) while the automatic program-
ming/erase operation is active and goes to
“
1
”
(READY) during the
other operations.
Bit 1 serves as the CPU reprogramming mode select bit. Writing of
“
1
”
to this bit selects the CPU reprogramming mode, and software
commands will be acceptable. Because the CPU cannot directly ac-
cess the internal flash memory in the CPU reprogramming mode,
writing to this bit 1 must be performed by the user-original repro-
gramming control software which has been transferred to the inter-
nal RAM in advance. To set bit 1 to
“
1
”
, it is necessary to write
“
0
”
and
“
1
”
to this bit 1 successively. On the other hand, to clear this bit to
“
0
”
,
it is sufficient only to write
“
0
”
.
Bit 2 serves as the lock bit invalidity select bit, and setting this bit to
“
1
”
invalidates the protection by a lock bit against erasing and pro-
gramming (block lock). The lock bit invalidity select bit can invali-
dates the lock bit function but set no lock bit itself. However, if erasing
is performed with this bit =
“
1
”
, a lock bit with value
“
0
”
(the locked
state) will be set to
“
1
”
(the unlocked state) after the erasing has
been completed. To set the lock bit invalidity select bit to
“
1
”
, write
“
0
”
and
“
1
”
to this bit 2 successively with the CPU reprogramming mode
select bit =
“
1
”
. The manipulation of bit 2 is allowed only when the
CPU reprogramming mode select bit =
“
1
”
.
Bit 3 (the flash memory reset bit) resets the control circuit of the in-
ternal flash memory and is used when the CPU reprogramming
mode is terminated or when an abnormal access to the flash
memory happens. Writing of
“
1
”
to bit 3 with the CPU reprogramming
mode select bit =
“
1
”
preforms the reset operation. To remove the
reset, write
“
0
”
to bit 3 subsequently.
Bit 5 serves as the user ROM area select bit and is valid only in the
boot mode. Setting this bit to
“
1
”
in the boot mode switches an acces-
sible area from the boot ROM area to the user ROM area. To use the
CPU reprogramming mode in the boot mode, set this bit to
“
1
”
. Note
that when the microcomputer is booted up in the user ROM area,
only the user ROM area is accessible and bit 5 is invalid; on the other
hand, when the microcomputer is in the boot mode, bit 5 is valid in-
dependent of the CPU reprogramming mode. To rewrite bit 5, ex-
ecute the user-original reprogramming control software transferred
to the internal RAM in advance.
Figure 115 shows the CPU reprogramming mode set/termination
flowchart, and be sure to follow this flowchart. As shown in Note 1 of
Figure 115, before selecting the CPU reprogramming mode, set the
processor mode register 1
’
s bit 7 (the internal ROM bus cycle select
bit) to
“
0
”
and set flag I to
“
1
”
to avoid an interrupt request input.
When an NMI interrupt or a watchdog timer interrupt request is gen-
erated in the CPU reprogramming mode, when an input to the
RESET pin is
“
L
”
, or when the software reset is performed, the flash
memory control circuit and flash memory control register will be re-
set.
When the flash memory is reset during the erase or programming
operation, this operation is cancelled and the target block
’
s data will
be invalid. Just before writing a software command related to the
erase/programming operation, be sure to write to the watchdog
timer. Also, be sure to set the NMI pin to
“
H
”
to avoid an NMI interrupt
request occurrence. In the CPU reprogramming mode, be sure not
to use the
STP
and
WIT
instructions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37902FGCGP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FCCHP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FGCHP | DIODE SCHOTTKY DUAL COMMON-ANODE 25V 150mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-523 3K/REEL |
| M37902FJCHP | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37905F8CFP | 16-BIT CMOS MICROCOMPUTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37902FCCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FGCGP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FGCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37902FJCHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37903S4CHP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:16-BIT CMOS MICROCOMPUTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。