參數(shù)資料
型號： M37902F8CHP
廠商： Mitsubishi Electric Corporation
英文描述： DIODE SCHOTTKY DUAL COMMON-ANODE 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-23 3K/REEL
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 140/143頁
文件大?。?/td> 1463K
代理商： M37902F8CHP
Corrections and
Page
Page 80,
L
e
f
t column,
Line 15
Page 80,
R
i
g
h
t column,
Line 1
Supplement
ar
Erro
y
Explanation
r
for M37902FxC Dat
asheet (REV.
Correction
B) NO.8
(8/11)
Page 81,
Fig. 83,
bits 1 and 0
1
Waveform out
11 :
RTP1 and RTP0
Whe
n
R
TP
p
ut
select bits
sel
ect
i
s
e
sel
d
pul
1 and RTP1
se
m
ode
0
ect
ed:
Page 86,
Fig. 91,
bi
t
s 2 to 0
Address/Port switch select bits
0 0 0 :
2 1 0
0
1
Waveform out
11 :
RTP1 and RTP0
Whe
n
R
TP
p
ut
select bits
sel
ect
i
s
e
sel
d
pul
1 and RTP0
se
m
ode
0
ect
ed:
0
Address/Port
0 0
0 :
sw
itch
bi
t
s
2 1 0
The D-A output enable bit is cleared to
“0”
at reset
.
The contents of
and D-A register
the corr
are cleared t
espond
ing D-A output
o “0”
at r
enab
le bit
eset.
wi
t
h pin D-Ai
.
wi
Al
the content
and D-A register
t
so,
h pin D-Ai
wh
.
ot
en
n
s of t
using
he
to “
the D-A convert
corresponding D-A output enable bit
0”.
e
r
, be sur
e to clear
[I
P4
0
/
n
side dott
A
LE, P4
1
/
φ
1
, P4
2
/HLDA
ed-li
ne
n
ot
incl
uded]
,
Page 87,
Fig. 89,
2nd diagram
[I
P4
0
/
n
side dott
A
LE, P4
1
/
φ
1
, P4
2
/HLDA
ed-li
ne
n
ot
incl
uded]
,
Port
l
at
ch
Output
Port latch
Out
put (Int
ern
al peripher
al devices)
Page 88,
Fig. 90,
3rd
di
agram
Page 89,
Fig. 93,
address 81
16
[Inside dotted-line not included]
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
[Inside dotted-line included]
P7
7
/AN
7
/AD
TRG
/DA
1
/(INT
2
)
Page 82,
Right column,
Lines 1 to 3
#
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), RTP1
3
to RTP1
0
and RTP0
3
to RTP0
0
become pulse output port pins.
When the waveform output
When the waveform output select bits are set to “11” (bit 1
= bit 0 = “1”), pulse output port pins are divided into two
groups; one consists of RTP1
3
to RTP1
0
, RTP0
3
, RTP0
2
and the other consists of RTP0
1
and RTP0
0
.
When the waveform output
Page 90,
Fig. 92,
address 70
16
0 0 0
A-D interrup
t
control register
(70
16
)
0 0 0
A-D conversion interr
u
pt
cont
rol
register
(
7
0
16
)
0 0 0
0
CS
0
control regi
st
er H
(81
16
)
0
0 0 0
0
CS
0
control regi
st
er H
(81
16
)
1
Page 91,
Left column,
Line 17
from
pin X
IN
and output a m
ultip
lied clock.
#
#
from pin X
IN
and generates a multiplied clock.
Page 91,
Left column,
Lines 11, 12
#
m
e
, the oscillatio
h
e
c
u
r
r
e
n
s
i
ci
p
r
t
cui
i
o
t
.
stops it’s o
p
e
r
a
t
i
o
n
a
n
d
r
e
s
u
-
s
t
n
t
d
i
s
a
n
c
u
r
, the oscillatio
n
t
d
i
s
s
i
p
n
s
ci
r
e
r
d
cui
u
t
e
stops it’s o
d
.
p
e
r
a
t
i
o
n
,
a
n
d
t
h
e
r
e
a
t
i
o
n
i
c
Page 92,
Right column,
Lines 4 to 5
not exceed 26 M
In t
h
is selection, be
Hz.
su
r
e that
multipl
ied f
(X
I
N
) does
fr
equ
range f
T
ency
rom
he
P
o
LL m
f
the PLL output
10
MHz to
ul
t
i
plication ratio m
ust be set
f
PLL
)
must
so that
be in the
the
cl
ock (
26
MHz.
Page 92,
Right column,
Lines 10 to 11
to “
the PLL
1”.)
output clock (
f
PL
L
)
. (
In other
words, set
bit 5
to “
select bits ar
the PLL
1”.) Note t
output clock (
h
at
, aft
e al
lowed to be
f
PL
t
L
)
h
ch
. (
e
anged only once.
In other
P
LL m
words, set
ul
t
i
plication ratio
bit 5
er r
ese
, t
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