參數(shù)資料
型號: M37902F8CHP
廠商: Mitsubishi Electric Corporation
英文描述: DIODE SCHOTTKY DUAL COMMON-ANODE 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-23 3K/REEL
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 28/143頁
文件大?。?/td> 1463K
代理商: M37902F8CHP
M37902FCCHP, M37902FGCHP, M37902FJCHP
MITSUBISHI MICROCOMPUTERS
28
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
G
Burst ROM access
When ROM supporting the burst ROM access has been allocated to
area CS
i
, the burst ROM access can be specified. The burst ROM
access is specified by each burst ROM access select bit of the CS
i
control register L (bit 5 at addresses 80
16
, 82
16
, 84
16
, 86
16
). The
burst ROM access is valid only when the external data bus width =
16 bits with an instruction prefetched. In the other cases, the normal
access is performed regardless of the contents of the burst ROM ac-
cess select bit. The burst ROM access can be specified only in the
case of
in Figure 18.
Figure 20 shows a waveform example at burst ROM access.
When an instruction is prefetched from the burst ROM, 8 bytes are
fetched starting from an 8-byte boundary (the low-order 3 bits of ad-
dress, A
2
, A
1
, A
0
=
000
) in waveform (a). When branched, regard-
less of the 8-byte boundary of the branch destination address,
access starting from the 4-byte boundary (the low-order 2 bits of ad-
dress, A
1
, A
0
=
00
) is performed in waveform (b). Once the 8-byte
boundary has been selected, instructions will be prefetched in wave-
form (a) until a branch.
Fig. 20 Waveform example at burst ROM access
Note:
The above is applied when 1 bus cycle = 2
φ
.
(b)
External address bus
(A
0
to A
23
)
RD
External data bus
(D
0
to D
7
)
Data
(Instruction)
External data bus
(D
8
to D
15
)
(Instruction)
Data
(Instruction)
(Instruction)
Address
Address
(a)
External address bus
(A
0
to A
23
)
RD
External data bus
(D
0
to D
7
)
Data
(Instruction)
External data bus
(D
8
to D
15
)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
φ
1
Address
Address
Address
Address
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
Data
(Instruction)
φ
1
A
A
Note:
The above is applied when 1 bus cycle = 2
φ
.
Notes 1:
The burst ROM access is selected by the burst ROM access select bit (bit 5 at addresses 80
16
, 82
16
, 84
16
, 86
16
).
2:
The burst ROM access can be selected only in the case of
in Figure 18.
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