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53
M37902FCCHP, M37902FGCHP, M37902FJCHP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When bit 2 of the timer Ai mode register is
“
1
”
, the output is gener-
ated from TAi
OUT
pin. The output is toggled each time the contents
of the counter reaches to 0000
16
. When the contents of the count
start bit is
“
0
”
,
“
L
”
is output from TAi
OUT
pin.
When bit 2 is
“
0
”
, TAi
OUT
can be used as a normal port pin. When bit
4 is
“
0
”
, TAi
IN
can be used as a normal port pin.
When bit 4 is
“
1
”
, counting is performed only while the input signal
from the TAi
IN
pin is
“
H
”
or
“
L
”
as shown in Figure 45. Therefore, this
can be used to measure the pulse width of the TAi
IN
input signal.
Whether to count while the input signal is
“
H
”
or while it is
“
L
”
is de-
termined by bit 3. If bit 3 is
“
1
”
, counting is performed while the TAi
IN
pin input signal is
“
H
”
and if bit 3 is
“
0
”
, counting is performed while it
is
“
L
”
.
Note that, the duration of
“
H
”
or
“
L
”
on the TAi
IN
pin must be 2 or
more cycles of the timer count source.
When data is written to timer Ai register with timer Ai halted, the
same data is also written to the reload register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The new data is reloaded
from the reload register to the counter at the next reload time and
counting continues. The contents of the counter can be read at any
time.
When the value set in the timer Ai register is n, the timer frequency
division ratio is 1/(n+1).
0 0 : Always
“
00
”
in timer mode
0 : No pulse output (TAi
OUT
is normal port pin.)
1 : Pulse output (TAi
OUT
is pulse output pin.)
(Note)
0
×
: No gate function (TAi
IN
is normal port pin.)
1 0 : Count only while TAi
IN
input is
“
L
”
.
1 1 : Count only while TAi
IN
input is
“
H
”
.
0 : Always
“
0
”
in timer mode.
Clock source select bits
See Table 12.
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
7
0
0
6
5
4
3
2
1
0
Addresses
56
16
57
16
58
16
59
16
5A
16
0
Note:
When using pins TA2
OUT
and TA3
OUT
as pulse output pins, do not select pins KI
0
and KI
2
.
Because they are key input interrupt pins and are multiplexed with pins TA2
OUT
and TA3
OUT
.
Fig. 43 Bit configuration of timer Ai mode register during timer mode
Fig. 42 Bit configuration of timer A clock division select register
Table 12. Relationship between timer A clock division select bits,
clock source select bits, and count source
Clock source select bits
(bits 7 and 6 at addresses
56
16
to 5A
16
)
0 0
0 1
f
16
f
64
1 1
f
512
Note:
Timers A0 to A4 use the same clock, which is selected by the
timer A clock division select bits.
Timer A clock division select bit
(See Table 12.)
7 6 5 4 3 2 1 0
Timer A clock division select register
Address
45
16
“
0
”
at read.
1 0
Timer A clock division select bits
(bits 1 and 0 at address 45
16
)
00
f
1
f
16
f
64
f
4096
f
2
01
f
1
f
64
f
512
f
4096
10
11
Do not
select.