參數(shù)資料
型號: M34551E8-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, MICROCONTROLLER, PQFP48
封裝: 7 X 10 MM, 0.65 MM PITCH, PLASTIC, QFP-48
文件頁數(shù): 72/154頁
文件大小: 1778K
代理商: M34551E8-XXXFP
FUNCTIONAL BLOCK OPERATIONS
4551 Group User’s Manual
HARDWARE
1-13
PROGRAM MEMORY (ROM)
1 word of ROM is composed of 10 bits. ROM is separated every
128 words by the unit of page (addresses 0 to 127). Table 1
shows the ROM size and pages. Figure 10 shows the ROM map
of M34551E8.
Table 1 ROM size and pages
Product
M34551M4
M34551M8
M34551E8
ROM size
(! 10 bits)
4096 words
8192 words
Pages
32 (0 to 31)
64 (0 to 63)
A top part of page 1 (addresses 008016 to 00FF16) is reserved
for interrupt addresses (Figure 11). When an interrupt occurs,
the address (interrupt address) corresponding to each interrupt
is set in the program counter, and the instruction at the interrupt
address is executed. When using an interrupt service routine,
write the instruction generating the branch to that routine at an
interrupt address.
Page 2 (addresses 010016 to 017F16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data
areas with the TABP p instruction.
Fig. 10 ROM map of M34551E8
90
87
654
3
2
1
Interrupt address page
000016
008016
017F16
Subroutine special page
007F16
00FF16
010016
1FFF16
018016
Page 1
Page 2
Page 0
Page 3
Page 63
0FFF16
Page 31
Fig. 11 Interrupt address page (addresses 008016 to 00FF16) structure
90
87
6
5
4
321
External 0 interrupt address
008016
008416
Timer 1 interrupt address
Timer 2 interrupt address
008616
00FF16
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