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1
1-23
OVERVIEW
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
1.4 Pin Assignments
Note 1: The pins outputted at two places.
Note 2: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.
Note 3: THERMAL BALL must be connected to the ground (GND).
Table 1.4.2 Pin Assignments of the M32192F8xWG (3/4)
Port Function 1
Function 2
DRI function
NBD function
Function
Type
State during
reset
State upon
exiting reset
During single-chip and
external extension modes
P01
Input
Hi-Z
During processor mode
DB1
Input/Output
Hi-Z
During single-chip and
external extension modes
P26
Input
Hi-Z
During processor mode
A29
Output
Hi-Z
Undefined
K5
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
K6
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
K7
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
K8
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
K9
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
K10
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
K11
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
K12
VSS
-
VSS
-
VSS
-
K13
P76/RTDACK/CTX1/NBDD2
P76
RTDACK CTX1 (Note 1)
NBDD2
Input/Output
VCCE
P76
Input
Hi-Z
K14
P77/RTDCLK/CRX1/NBDD3
P77
RTDCLK CRX1 (Note 1)
NBDD3
Input/Output
VCCE
P77
Input
Hi-Z
K15
P93/TO16/SCLKI5/SCLKO5
P93
TO16
SCLKI5/
SCLKO5
-
Input/Output
VCCE
P93
Input
Hi-Z
During single-chip and
external extension modes
P03
Input
Hi-Z
During processor mode
DB3
Input/Output
Hi-Z
During single-chip and
external extension modes
P04
Input
Hi-Z
During processor mode
DB4
Input/Output
Hi-Z
During single-chip and
external extension modes
P05
Input
Hi-Z
During processor mode
DB5
Input/Output
Hi-Z
During single-chip and
external extension modes
P02
Input
Hi-Z
During processor mode
DB2
Input/Output
Hi-Z
L5
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
L6
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
L7
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
L8
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
L9
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
L10
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
L11
THERMAL-BALL (Note 3)
-
VSS
-
VSS
-
L12
N.C.
-
--
-
--
-
L13
P73/HACK#/TIN26
P73
HACK#
TIN26
-
Input/Output
VCCE
P73
Input
Hi-Z
L14
P74/RTDTXD/TXD3/NBDD0
P74
RTDTXD TXD3 (Note 1)
NBDD0
Input/Output
VCCE
P74
Input
Hi-Z
L15
P75/RTDRXD/RXD3/NBDD
P75
RTDRXD RXD3 (Note 1)
NBDD1
Input/Output
VCCE
P75
Input
Hi-Z
During single-chip and
external extension modes
P06
Input
Hi-Z
During processor mode
DB6
Input/Output
Hi-Z
During single-chip and
external extension modes
P07
Input
Hi-Z
During processor mode
DB7
Input/Output
Hi-Z
During single-chip and
external extension modes
P10
Input
Hi-Z
During processor mode
DB8
Input/Output
Hi-Z
M4
VREF0
-
VREF0
-
AVCC0
VREF0
-
M5
AD0IN2
-
AD0IN2
-
Input
AVCC0
AD0IN2
Input
Hi-Z
M6
AD0IN6
-
AD0IN6
-
Input
AVCC0
AD0IN6
Input
Hi-Z
M7
AD0IN10
-
AD0IN10
-
Input
AVCC0
AD0IN10
Input
Hi-Z
M8
AD0IN14
-
AD0IN14
-
Input
AVCC0
AD0IN14
Input
Hi-Z
M9
AD0IN15
-
AD0IN15
-
Input
AVCC0
AD0IN15
Input
Hi-Z
M10
N.C.
-
--
-
--
-
M11
P174/TXD2/TO28
P174
TXD2
TO28 (Note 1)
-Input/Output
VCCE
P174
Input
Hi-Z
M12
VCCE
-
VCCE
-
VCCE
-
M13
P70/CLKOUT/WR#/BCLK
P70
CLKOUT/
WR#
BCLK
-
Input/Output
VCCE
P70
Input
Hi-Z
M14
P71/WAIT#
P71
WAIT#
-
Input/Output
VCCE
P71
Input
Hi-Z
M15
P72/HREQ#/TIN27
P72
HREQ#
TIN27
-
Input/Output
VCCE
P72
Input
Hi-Z
During single-chip and
external extension modes
P11
Input
Hi-Z
During processor mode
DB9
Input/Output
Hi-Z
During single-chip and
external extension modes
P12
Input
Hi-Z
During processor mode
DB10
Input/Output
Hi-Z
During single-chip and
external extension modes
P15
Input
Hi-Z
During processor mode
DB13
Input/Output
Hi-Z
N4
N.C.
-
N5
AVCC0
-
AVCC0
-
AVCC0
-
N6
AD0IN3
-
AD0IN3
-
Input
AVCC0
AD0IN3
Input
Hi-Z
N7
AD0IN7
-
AD0IN7
-
Input
AVCC0
AD0IN7
Input
Hi-Z
N8
AD0IN11
-
AD0IN11
-
Input
AVCC0
AD0IN11
Input
Hi-Z
N9
VSS
-
VSS
-
VSS
-
N10
N.C.
-
--
-
--
-
N11
P82/TXD0/TO26
P82
TXD0
TO26 (Note 1)
-Input/Output
VCCE
P82
Input
Hi-Z
N12
P85/TXD1/TO23
P85
TXD1
TO23 (Note 1)
-Input/Output
VCCE
P85
Input
Hi-Z
N13
P87/SCLKI1/
SCLKO1/TO21
P87
SCLKI1/
SCLKO1
TO21 (Note 1)
-
Input/Output
VCCE
P87
Input
Hi-Z
N14
P63
-
Input/Output
VCCE
P63
Input
Hi-Z
N15
SBI#
-
Input
VCCE
SBI#
Input
Hi-Z
P1
N.C.
-
During single-chip and
external extension modes
P13
Input
Hi-Z
During processor mode
DB11
Input/Output
Hi-Z
During single-chip and
external extension modes
P16
Input
Hi-Z
During processor mode
DB14
Input/Output
Hi-Z
During single-chip and
external extension modes
P17
Input
Hi-Z
During processor mode
DB15
Input/Output
Hi-Z
P5
AD0IN0
-
AD0IN0
-
Input
AVCC0
AD0IN0
Input
Hi-Z
P6
AD0IN4
-
AD0IN4
-
Input
AVCC0
AD0IN4
Input
Hi-Z
P7
AD0IN8
-
AD0IN8
-
Input
AVCC0
AD0IN8
Input
Hi-Z
P8
AD0IN12
-
AD0IN12
-
Input
AVCC0
AD0IN12
Input
Hi-Z
Pin No.
Symbol
Function
Type
Power
supply
Condition
Pin state when reset
K3
P01/DB1/TO22/DD1
P01
DB1
TO22 (Note 1) DD1 (Note 1) Input/Output VCC-BUS
K4
P26/A29/DD30
P26
A29
-
DD30
Input/Output VCC-BUS
L1
P03/DB3/TO24/DD3
P03
DB3
TO24 (Note 1) DD3 (Note 1) Input/Output VCC-BUS
L2
P04/DB4/TO25/DD4
P04
DB4
TO25 (Note 1) DD4 (Note 1) Input/Output VCC-BUS
L3
P05/DB5/TO26/DD5
P05
DB5
TO26 (Note 1) DD5 (Note 1) Input/Output VCC-BUS
L4
P02/DB2/TO23/DD2
P02
DB2
TO23 (Note 1) DD2 (Note 1) Input/Output VCC-BUS
M1
P06/DB6/TO27/DD6
P06
DB6
TO27 (Note 1) DD6 (Note 1) Input/Output VCC-BUS
M2
P07/DB7/TO28/DD7
P07
DB7
TO28 (Note 1) DD7 (Note 1) Input/Output VCC-BUS
M3
P10/DB8/TO29/DD8
P10
DB8
TO29 (Note 1) DD8 (Note 1) Input/Output VCC-BUS
N1
P11/DB9/TO30/DD9
P11
DB9
TO30 (Note 1) DD9 (Note 1) Input/Output VCC-BUS
N2
P12/DB10/TO31/DD10
P12
DB10
TO31 (Note 1) DD10 (Note 1) Input/Output VCC-BUS
N3
P15/DB13/TO34/DD13
P15
DB13
TO34 (Note 1) DD13 (Note 1) Input/Output VCC-BUS
P2
P13/DB11/TO32/DD11
P13
DB11
TO32 (Note 1) DD11 (Note 1) Input/Output VCC-BUS
P3
P16/DB14/TO35/DD14
P16
DB14
TO35 (Note 1) DD14 (Note 1) Input/Output VCC-BUS
P4
P17/DB15/TO36/DD15
P17
DB15
TO36 (Note 1) DD15 (Note 1) Input/Output VCC-BUS