參數(shù)資料
型號: LH7A400N0G000B5
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A400N0F000B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT1020-1.html<1<Always Pb-free,;LH7A400N0F076B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 8/65頁
文件大?。?/td> 834K
代理商: LH7A400N0G000B5
LH7A400
32-Bit System-on-Chip
8
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
D13
E11
A12
C12
C11
F9
A9
B9
D9
E9
A15
D11
E10
A13
B11
C11
C9
A9
B9
A8
nSCS1
nSCS2
nSCS3
nSWE
nCAS
nRAS
DQM0
DQM1
DQM2
DQM3
Sync Memory Chip Select 1
Sync Memory Chip Select 2
Sync Memory Chip Select 3
Sync Memory Write Enable
Sync Memory Column Address Strobe Signal
Sync Memory Row Address Strobe Signal
Sync Memory Data Mask 0
Sync Memory Data Mask 1
Sync Memory Data Mask 2
Sync Memory Data Mask 3
GPIO Port A
LCD Data bit 16. This CLCDC output signal is
always LOW.
GPIO Port A
LCD Data bit 17. This CLCDC output signal is
always LOW.
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
O
O
O
O
O
O
O
O
O
O
J5
K1
PA0/LCDVD16
Input: PA0
No Change
8 mA
I/O
K1
K2
PA1/LCDVD17
Input: PA1
No Change
8 mA
I/O
K2
K3
K5
L1
L2
L3
K3
K4
K6
K5
L1
L2
PA2
PA3
PA4
PA5
PA6
PA7
PB0/
UARTRX1
GPIO Port A
Input
No Change
8 mA
I/O
I/O
I/O
I/O
I/O
I/O
L4
L3
GPIO Port B
UART1 Receive Data Input
Input: PB0
No Change
8 mA
I/O
L5
M1
PB1/UARTTX3
GPIO Port B
UART3 Transmit Data Out
Input: PB1
LOW if
PINMUX:
UART3CON
= 1 (bit 3);
otherwise
No Change
8 mA
I/O
L7
M2
PB2/
UARTRX3
PB3/
UARTCTS3
PB4/
UARTDCD3
PB5/
UARTDSR3
GPIO Port B
UART3 Receive Data In
GPIO Port B
UART3 Clear to Send
GPIO Port B
UART3 Data Carrier Detect
GPIO Port B
UART3 Data Set Ready
GPIO Port B
Single Wire Data
Smart Battery Data
GPIO Port B
Smart Battery Clock
GPIO Port C
UART1 Transmit Data Output
GPIO Port C
HR-TFT Power Save
GPIO Port C
HR-TFT Power Sequence Control
GPIO Port C
HR-TFT Gray Scale Voltage Reverse
GPIO Port C
HR-TFT Reset Row Driver Counter
Input: PB2
No Change
8 mA
I/O
M2
M3
Input: PB3
No Change
8 mA
I/O
M4
L5
Input: PB4
No Change
8 mA
I/O
N1
N1
Input: PB5
No Change
8 mA
I/O
N2
N2
PB6/SWID/
SMBD
Input: PB6
No Change
8 mA
I/O
N3
M4
PB7/
SMBCLK
PC0/
UARTTX1
Input: PB7
No Change
8 mA
I/O
7
P1
P1
LOW: PC0
No Change
12 mA
I/O
P2
P2
PC1/LCDPS
LOW: PC1
No Change
12 mA
I/O
R1
R1
PC2/
LCDVDDEN
LOW: PC2
No Change
12 mA
I/O
K6
M5
PC3/LCDREV
LOW: PC3
No Change
12 mA
I/O
L8
P3
PC4/
LCDSPS
LOW: PC4
No Change
12 mA
I/O
Table 3. Functional Pin List (Cont’d)
BGA
PIN
LFBGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
I/O NOTES
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LH7A400N0W000 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:32-Bit System-on-Chip