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| 型號(hào)： | LH7A400N0G000B5 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | 32-Bit System-on-Chip |
| 封裝： | LH7A400N0F000B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT1020-1.html<1<Always Pb-free,;LH7A400N0F076B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT |
| 文件頁(yè)數(shù)： | 54/65頁(yè) |
| 文件大?。?/td> | 834K |
| 代理商： | LH7A400N0G000B5 |
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LH7A400
32-Bit System-on-Chip
54
Rev. 01
—
16 July 2007
Preliminary data sheet
NXP Semiconductors
CLOCK AND STATE CONTROLLER (CSC)
WAVEFORMS
Figure 42 shows the behavior of the LH7A400 when
coming out of Reset or Power On. Figure 43 shows exter-
nal reset timing, and Table 13 gives the timing parame-
ters. Figure 44 depicts signal timing following a Reset.
At Power-On, nPOR must be held LOW at least until
the 32.768 kHz oscillator is stable, and must be deas-
serted at least two 32.768 kHz clock periods before the
WAKEUP signal is asserted. Once the 14.7456 MHz
oscillator is stable, the PLLs require 250
μ
s
to lock.
On transition from Standby to Run (including a Cold
Boot), the Wakeup pin must not be asserted for 2 sec-
onds after assertion of nPOR to allow time for sampling
BATOK and nEXTPWR. The delay prevents a false
‘battery good’ indication caused by alkaline battery
recovery that can immediately follow a battery-low
switch off. The battery sampling takes place on the ris-
ing edge of the 1 Hz clock. This clock is derived from
the 32.768 kHz oscillator. The WAKEUP pin can be
pulsed, but at least one edge must follow the 2 second
delay to be recognized. For more information, see the
application note “Implementing Auto-Wakeup on the
LH7A4xx Series Devices” at www.nxp.com.
Figure 45 shows the recommended components for
the NXP LH7A400 32.768 kHz external oscillator cir-
cuit. Figure 46 shows the same for the 14.7456 MHz
external oscillator circuit. In both figures, the NAND
gate represents the internal logic of the chip.
NOTE:
*VDDC = VDDCmin
Figure 41. AD-TFT and HR-TFT Vertical Timing Diagram
LCDSPS
(Vertical Sync)
LCDHRLP
(Horizontal Sync)
LCDVD
(LCD Data)
LCDSPL
LH7A400-66
TIMING1:VSW
1.5 μs - 4 μs
2x H-LINE
L8
T2
R2
Table 13. Reset AC Timing
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT
tOSC32
32.768 kHz Oscillator Stabilization Time after Power On*
550
ms
tOSC14
14.7456 MHz Oscillator Stabilization Time after Wake UP
4
ms
tURESET/tPWRFL
nURESET/nPWRFL Pulse Width
4
32.768 kHz clock periods
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH7A400N0G000B5,55 | 功能描述:ARM微控制器 - MCU LCD,USB FS/HOST,MMU,ADC,BGA324 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A400N0G000B5,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A400N0G000B5;55 | 功能描述:ARM微控制器 - MCU LCD USB FS/HOST MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A400N0G000B5-S | 功能描述:ARM微控制器 - MCU ARM9 LCD USB HOST RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH7A400N0W000 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:32-Bit System-on-Chip |
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