參數(shù)資料
型號: KSZ8851SNL-EVAL
廠商: Micrel Inc
文件頁數(shù): 51/80頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8851SNL
產(chǎn)品培訓模塊: KSZ8851 10/100 Embedded Controllers
標準包裝: 1
系列: LinkMD®
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8851SNL
主要屬性: 1 個端口,100BASE-TX/10BASE-T
次要屬性: SPI 接口,LinkMD 線纜診斷
已供物品: 板,文檔
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
相關產(chǎn)品: 576-3299-6-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-1-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-2-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3254-ND - IC CTLR MAC/PHY NON-PCI 32-QFN
其它名稱: 576-3293
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
55
M9999-083109-2.0
0x88 – 0x8B: Reserved
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR
This register is used to program the received frame duration timer threshold.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
RXDTT Receive Duration Timer Threshold
To program received frame duration timer threshold value in 1us interval. The maximum value is
0xCFFF.
When bit 7 set to 1 in RXQCR register, the KSZ8851SNL will set RX interrupt (bit 13 in ISR) after
the time starts at first received frame in RXQ buffer and exceeds the threshold set in this register.
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR
This register is used to program the received data byte count threshold.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
RXDBCT Receive Data Byte Count Threshold
To program received data byte threshold value in byte count.
When bit 6 set to 1 in RXQCR register, the KSZ8851SNL will set RX interrupt (bit 13 in ISR)
when the number of received bytes in RXQ buffer exceeds the threshold set in this register.
Interrupt Enable Register (0x90 – 0x91): IER
This register enables the interrupts from the QMU and other sources.
Bit
Default Value
R/W
Description
15
0x0
RW
LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
14
0x0
RW
TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
13
0x0
RW
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
12
0x0
RW
Reserved
11
0x0
RW
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
10
0x0
RW
Reserved
9
0x0
RW
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
8
0x0
RW
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
7
0x0
RW
Reserved
6
0x0
RW
TXSAIE Transmit Space Available Interrupt Enable
When this bit is set, the Transmit memory space available interrupt is enabled.
When this bit is reset, the Transmit memory space available interrupt is disabled.
5
0x0
RW
RXWFDIE Receive Wake-up Frame Detect Interrupt Enable
When this bit is set, the Receive wakeup frame detect interrupt is enabled.
When this bit is reset, the Receive wakeup frame detect interrupt is disabled.
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