參數(shù)資料
型號: KSZ8851SNL-EVAL
廠商: Micrel Inc
文件頁數(shù): 39/80頁
文件大小: 0K
描述: BOARD EVALUATION KSZ8851SNL
產(chǎn)品培訓模塊: KSZ8851 10/100 Embedded Controllers
標準包裝: 1
系列: LinkMD®
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8851SNL
主要屬性: 1 個端口,100BASE-TX/10BASE-T
次要屬性: SPI 接口,LinkMD 線纜診斷
已供物品: 板,文檔
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3299-6-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-1-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3299-2-ND - IC CTLR MAC/PHY NON-PCI 32-MLF
576-3254-ND - IC CTLR MAC/PHY NON-PCI 32-QFN
其它名稱: 576-3293
Micrel, Inc.
KSZ8851SNL/SNLI
August 2009
44
M9999-083109-2.0
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0CRC0
Wake up Frame 0 CRC (lower 16 bits)
The expected CRC value of a Wake up frame 0 pattern.
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1
This register contains the expected CRC values of the Wake up frame 0 pattern.
The value of the CRC calculated is based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in
the wake up byte mask registers.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0CRC1
Wake up Frame 0 CRC (upper 16 bits).
The expected CRC value of a Wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0
This register contains the first 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the first byte
of the Wake up frame 0, setting bit 15 selects the 16th byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM0
Wake up Frame 0 Byte Mask 0
The first 16 bytes mask of a Wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 0. Setting bit 15 selects the 32nd byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM1
Wake up Frame 0 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake up frame 0 pattern.
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 0. Setting bit 15 selects the 48th byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM2
Wake-up Frame 0 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a Wake-up frame 0 pattern.
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3
This register contains the last 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 0. Setting bit 15 selects the 64th byte of the Wake up frame 0.
Bit
Default Value
R/W
Description
15-0
0x0000
RW
WF0BM3
Wake-up Frame 0 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame 0 pattern.
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