- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369586 > KC80524NY450128 Microprocessor PDF資料下載
參數(shù)資料
| 型號： | KC80524NY450128 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 72/81頁 |
| 文件大小： | 598K |
| 代理商： | KC80524NY450128 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁當前第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
72
RP# (I/O - GTL+)
The RP# (Request Parity) signal is driven by the request initiator and provides parity protection on
ADS# and REQ[4:0]#. RP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low and low if an odd
number of covered signals are low. This definition allows parity to be high when all covered
signals are high.
RS[2:0]# (I - GTL+)
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for
completion of the current transaction) and must be connected to the appropriate pins/balls on both
agents on the system bus.
RSP# (I - GTL+)
The RSP# (Response Parity) signal is driven by the response agent (the agent responsible for
completion of the current transaction) during assertion of RS[2:0]#. RSP# provides parity
protection for RS[2:0]#. RSP# should be connected to the appropriate pins/balls on both agents on
the system bus.
A correct parity signal is high if an even number of covered signals are low, and it is low if an odd
number of covered signals are low. During Idle state of RS[2:0]# (RS[2:0]#=000), RSP# is also
high since it is not driven by any agent guaranteeing correct parity.
RSVD (TBD)
The RSVD (Reserved) signal is currently unimplemented but is reserved for future use. Leave this
signal unconnected. Intel recommends that a routing channel for this signal be allocated.
RTTIMPEDP (Analog)
The RTTIMPEDP (R
TT
Impedance/PMOS) signal is used to configure the on-die GTL+
termination. Connect the RTTIMPEDP signal to V
SS
with a 56.2-
, 1% resistor.
SLP# (I - 1.5V Tolerant)
The SLP# (Sleep) signal, when asserted in the Stop Grant state, causes the processor to enter the
Sleep state. During the Sleep state, the processor stops providing internal clock signals to all units,
leaving only the Phase-Locked Loop (PLL) still running. The processor will not recognize snoop
and interrupts in the Sleep state. The processor will only recognize changes in the SLP#,
STPCLK# and RESET# signals while in the Sleep state. If SLP# is deasserted, the processor exits
Sleep state and returns to the Stop Grant state in which it restarts its internal clock to the bus and
APIC processor units.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KP80524NY450128 | Microprocessor |
| RH8053GC017512 | Microprocessor |
| RH8053GC021512 | Microprocessor |
| RH8053GC025512 | Microprocessor |
| RH8053GC029512 | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KC80526GY001256S L54F | 制造商:Intel 功能描述:MPU Pentium |
| KC80526GY650256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| KC80526GY6504JY | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| KC80526GY850256S L547 | 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 64-Bit 0.18um 850MHz 495-Pin BGA2 |
| KC80526GY850256SL547 | 功能描述:IC PENTIUM 3 1.6V 850MHZ 495-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。