參數(shù)資料
型號(hào)： KC80524NY450128
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 68/81頁(yè)
文件大?。?/td> 598K
代理商： KC80524NY450128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
68
appropriate pins/balls on both agents on the system bus if they are used. During power-on
configuration, DEP[7:0]# signals can be enabled for ECC checking or disabled for no checking.
DRDY# (I/O - GTL+)
The DRDY# (Data Ready) signal is asserted by the data driver on each data transfer, indicating
valid data on the data bus. In a multi-cycle data transfer, DRDY# can be deasserted to insert idle
clocks. This signal must be connected to the appropriate pins/balls on both agents on the system
bus.
EDGCTRLP (Analog)
The EDGCTRLP (Edge Rate Control) signal is used to configure the edge rate of the GTL+ output
buffers. Connect the signal to V
SS
with a 110-
, 1% resistor.
FERR# (O - 1.5V Tolerant Open-drain)
The FERR# (Floating-point Error) signal is asserted when the processor detects an unmasked
floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and it
is included for compatibility with systems using DOS-type floating-point error reporting.
FLUSH# (I - 1.5V Tolerant)
When the FLUSH# (Flush) input signal is asserted, the processor writes back all internal cache
lines in the Modified state and invalidates all internal cache lines. At the completion of a flush
operation, the processor issues a Flush Acknowledge transaction. The processor stops caching any
new data while the FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each processor bus agent samples FLUSH# to
determine its power-on configuration.
HIT# (I/O - GTL+), HITM# (I/O - GTL+)
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop operation
results, and must be connected to the appropriate pins/balls on both agents on the system bus.
Either bus agent can assert both HIT# and HITM# together to indicate that it requires a snoop
stall, which can be continued by reasserting HIT# and HITM# together.
IERR# (O - 1.5V Tolerant Open-drain)
The IERR# (Internal Error) signal is asserted by the processor as the result of an internal error.
Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the system bus.
This transaction may optionally be converted to an external error signal (e.g., NMI) by system
logic. The processor will keep IERR# asserted until it is handled in software or with the assertion
of RESET#, BINIT, or INIT#.
相關(guān)PDF資料
PDF描述
KP80524NY450128 Microprocessor
RH8053GC017512 Microprocessor
RH8053GC021512 Microprocessor
RH8053GC025512 Microprocessor
RH8053GC029512 Microprocessor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KC80526GY001256S L54F 制造商:Intel 功能描述:MPU Pentium
KC80526GY650256 制造商:Rochester Electronics LLC 功能描述:- Bulk
KC80526GY6504JY 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述:
KC80526GY850256S L547 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 64-Bit 0.18um 850MHz 495-Pin BGA2
KC80526GY850256SL547 功能描述:IC PENTIUM 3 1.6V 850MHZ 495-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*