參數(shù)資料
型號(hào)： KC80524NY450128
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 66/81頁(yè)
文件大?。?/td> 598K
代理商： KC80524NY450128
Mobile Intel
Celeron Processor (0.18μ) in BGA2 and Micro-PGA2 Packages
Datasheet
Order Number#249563-001
66
BNR# (I/O - GTL+)
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus agent that is unable
to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new
transactions.
Since multiple agents may need to request a bus stall simultaneously, BNR# is a wired-OR signal
that must be connected to the appropriate pins/balls of both agents on the system bus. In order to
avoid wire-OR glitches associated with simultaneous edge transitions driven by multiple drivers,
BNR# is activated on specific clock edges and sampled on specific clock edges.
BP[3:2]# (I/O - GTL+)
The BP[3:2]# (Breakpoint) signals are the System Support group Breakpoint signals. They are
outputs from the processor that indicate the status of breakpoints.
BPM[1:0]# (I/O - GTL+)
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance monitor signals.
They are outputs from the processor that indicate the status of breakpoints and programmable
counters used for monitoring processor performance.
BPRI# (I - GTL+)
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the system bus. It
must be connected to the appropriate pins/balls on both agents on the system bus. Observing
BPRI# active (as asserted by the priority agent) causes the processor to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed and then releases the bus by deasserting BPRI#.
BREQ0# (I/O - GTL+)
The BREQ0# (Bus Request) signal is a processor Arbitration Bus signal. The processor indicates
that it wants ownership of the system bus by asserting the BREQ0# signal.
During power-up configuration, the central agent must assert the BREQ0# bus signal. The
processor samples BREQ0# on the active-to-inactive transition of RESET#.
BSEL[1:0] (I - 3.3V Tolerant)
The BSEL[1:0] (Select Processor System Bus Speed) signal is used to configure the processor for
the system bus frequency. Table 35 shows the encoding scheme for BSEL[1:0]. The only
supported system bus frequency for the mobile Intel Celeron processor is 100 MHz. If another
frequency is used or if the BSEL[1:0] signals are not driven with “01” then the processor is not
guaranteed to function properly.
相關(guān)PDF資料
PDF描述
KP80524NY450128 Microprocessor
RH8053GC017512 Microprocessor
RH8053GC021512 Microprocessor
RH8053GC025512 Microprocessor
RH8053GC029512 Microprocessor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KC80526GY001256S L54F 制造商:Intel 功能描述:MPU Pentium
KC80526GY650256 制造商:Rochester Electronics LLC 功能描述:- Bulk
KC80526GY6504JY 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述:
KC80526GY850256S L547 制造商:Intel 功能描述:MPU Pentium 制造商:Intel 功能描述:MPU Pentium? III Processor 64-Bit 0.18um 850MHz 495-Pin BGA2
KC80526GY850256SL547 功能描述:IC PENTIUM 3 1.6V 850MHZ 495-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:- 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*