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參數(shù)資料
| 型號： | K4B4G0846B-MCF80 |
| 元件分類： | DRAM |
| 英文描述： | 512M X 8 DDR DRAM, 0.3 ns, PBGA78 |
| 封裝： | HALOGEN FREE AND ROHS COMPLIANT, FBGA-78 |
| 文件頁數(shù)： | 8/59頁 |
| 文件大?。?/td> | 1079K |
| 代理商： | K4B4G0846B-MCF80 |
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Page 16 of 59
Rev. 1.0 March 2009
DDP 4Gb DDR3 SDRAM
K4B4G0446B
K4B4G0846B
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle
preceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK .
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode charateristics of these signals.
[ Table 11 ] Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Notes:
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
Symbol
Parameter
DDR3-800/1066/1333/1600
Unit
Notes
Min
Max
VSEH
Single-ended high-level for strobes
(VDD/2)+0.175
Note3
V
1, 2
Single-ended high-level for CK, CK
(VDD/2)+0.175
Note3
V
1, 2
VSEL
Single-ended low-level for strobes
Note3
(VDD/2)-0.175
V1, 2
Single-ended low-level for CK, CK
Note3
(VDD/2)-0.175
V1, 2
VDD or VDDQ
VSEH min
VDD/2 or VDDQ/2
VSEL max
VSEH
VSS or VSSQ
VSEL
CK or DQS
time
Figure 3 : Single-ended requirement for differential signals.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4B4G0846B-MCH9 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDP 4Gb B-die DDR3 SDRAM Specification |
| K4B4G0846D-BCK0000 | 制造商:Samsung Semiconductor 功能描述: |
| K4B4G1646B-HCH9000 | 制造商:Samsung Semiconductor 功能描述: |
| K4B4G1646B-HCK000 | 制造商:Samsung Semiconductor 功能描述: |
| K4B4G1646B-HCK0000 | 制造商:Samsung 功能描述:DDR SGRAM X16 TSOP2 - Trays |
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