參數(shù)資料
型號： K4B4G0846B-MCF80
元件分類： DRAM
英文描述： 512M X 8 DDR DRAM, 0.3 ns, PBGA78
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
文件頁數(shù)： 21/59頁
文件大?。?/td> 1079K
代理商： K4B4G0846B-MCF80
Page 28 of 59
Rev. 1.0 March 2009
DDP 4Gb DDR3 SDRAM
K4B4G0446B
K4B4G0846B
10.0 IDD Specification Parameters and Test Conditions
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
IDDQ measurements.
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
IDD currents.
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied
together. Any IDD current is not included in IDDQ currents.
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ
are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply :
- "0" and "LOW" is defined as VIN <= VILAC(max).
- "1" and "HIGH" is defined as VIN >= VIHAC(min).
- "FLOATING" is defined as inputs are VREF = VDD / 2.
- Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 30.
- Basic IDD and IDDQ Measurement Conditions are described in Table 31.
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 33 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
Timing parameters are listed in the following table:
[ Table 30 ] Timing used for IDD and IDDQ Measured-Loop Patterns.
Parameter Bin
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Unit
5-5-5
6-6-6
7-7-7
8-8-8
7-7-7
8-8-8
9-9-9
10-10-10
8-8-8
9-9-9
10-10-10
11-11-11
tCKmin(IDD)
2.5
1.875
1.5
1.25
ns
CL(IDD)
5
6
7
8
7
8
9
10
8
9
10
11
nCK
tRCDmin(IDD)
5
6
7
8
7
8
9
10
8
9
10
11
nCK
tRCmin(IDD)
2021
26272831
32
33
34
36
37
38
39
nCK
tRASmin(IDD)
15
20
24
28
nCK
tRPmin(IDD)
5
66
78
789
10
89
10
11
nCK
tFAW(IDD)
x4/x8
16
20
24
nCK
x16
20
27
30
32
nCK
tRRD(IDD)
x4/x8
4
5
nCK
x16
4
6
5
6
nCK
tRFC(IDD) - 512Mb
36
48
60
72
nCK
tRFC(IDD) - 1Gb
44
59
74
88
nCK
tRFC(IDD) - 2Gb
64
86
107
128
nCK
tRFC(IDD) - 4Gb
120
160
200
240
nCK
tRFC(IDD) - 8Gb
140
187
234
280
nCK
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4B4G0846B-MCH9 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:DDP 4Gb B-die DDR3 SDRAM Specification
K4B4G0846D-BCK0000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCH9000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK000 制造商:Samsung Semiconductor 功能描述:
K4B4G1646B-HCK0000 制造商:Samsung 功能描述:DDR SGRAM X16 TSOP2 - Trays
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