參數(shù)資料
型號(hào)： IS43R32800B-5BL
廠(chǎng)商： INTEGRATED SILICON SOLUTION INC
元件分類(lèi)： DRAM
英文描述： 8M X 32 DDR DRAM, 0.7 ns, PBGA144
封裝： 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-144
文件頁(yè)數(shù)： 9/39頁(yè)
文件大?。?/td> 507K
代理商： IS43R32800B-5BL
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. 00D
03/19/08
IS43R32800B
Notes
1. Al l voltagesreferenced to Vss.
2. Testsfor AC timing,I DD, andelectrical, AC andDCcharacteristics,may be conductedatnominal reference/supply
voltagelevels,but therelated specifications anddeviceoperationare guaranteed forthe full voltagerangespecified.
3. AC timing andIDD testsmay usea VI LtoV IH swingofupto1.5Vi nthe test environment, butinputtimingisstill
referenced to VR EF (ortothe crossing pointfor CK //CK), andparameter specifications are guaranteedforthe
specified AC inputlevelsunder normal useconditions. Theminimum slew rate forthe inputsignalsis1V/ns in the
rangebetweenV IL (AC) andVIH (AC) .
4. TheACand DC inputlevel specifications areasdefined in theSST L_ 2Standard (i.e.the receiver will effectively
switchasa result of thesignalcrossingthe AC inputlevel,and will remain in that stateaslongasthe signal does not
ring back above(below) theDCi nput LO W( HI GH )level.
5. VR EF is expected to be equalto0.5*VDDQ of thetransmittingdevice, andtotrack variations in theDCl evel of the
same.Peak-to-peaknoise on VR EF maynot exceed +2% of theDCvalue.
6. VT Ti snot applieddirectly to thedevice. VT Ti sa system supplyfor signal terminationresistors,isexpected to be
setequaltoV RE F, andmusttrack variations in theDCl evel of VR EF .
7. VI Di sthe magnitude of thedifferencebetween theinput levelonCLK andthe inputlevelon/CL K.
8. Thevalue of VI Xi sexpected to equal0.5*VDDQ ofthe transmitting device andmusttrack variations in theDCl evel
of thesame.
9. Enableson-chip refreshand addresscounters.
10. ID Dspecifi cations aretestedafter thedeviceisproperlyinitialized.
11. This parameterissampled.V DDQ =2.5V+ 0.2V ,V DD =2.5V+ 0.2V ,f = 100 MH z, Ta =25oC, VO UT (DC) =
VDDQ/2,V OUT( PE AK TO PE AK )= 25mV .DMi nputsare groupedwithI/O pins -reflectingthe fact that they are
matchedinloading (tofacili tatetracematchingatthe boardlevel).
12. TheCLK// CL Ki nput referencelevel (for timingreferenced to CL K //CLK )isthe pointatwhich CL Ka nd /CLK
cross; theinputreferencelevel forsignals otherthanCLK// CL K, is VR EF .
13. Inputsare notrecognized as valid untilV RE Fstabili zes. Ex ception: during theperiodbeforeV RE Fstabilizes,
CKE< 0.3VDDQ is recognized as LOW.
14. tHZand tLZtransitions occurinthe same access time windowsasvalid data transitions.T hese parameters arenot
referenced to aspecificvoltagelevel, butspecify when thedeviceoutputis no longer driving(HZ ), or begins driving
(LZ) .
15. Themaximum limit forthisparameter is nota device limit. Thedevicewill operatewitha greatervalue forthis
parameter, butsystemperformance (bus turnaround) will degradeaccordingly.
16. Thespecificrequirement is that DQS be valid(HI GH ,L OW ,oratsomepoint on avalid transition)onorbefore
this CL Ke dge.A validtransitionisdefined as monotonic, andmeetingthe inputslew rate specifications of thedevice.
When no writeswerepreviouslyinprogressonthe bus, DQSwillbetransitioning from Hi gh-Z to logicL OW .I fa
previous write wasinprogress, DQS couldbeHIG H, LOW, or transitioning from HI GH to LO Watthistime,
dependingontDQSS.
17. Amaximum of eightAUT OR EF RE SH commands can be posted to anygiven DDR SD RA Mdevice.
18. tXPR Dshouldbe 200 tCLK in theconditionofthe unstable CL Ko peration during thepower down mode.
19. Forcommand/addressand CK &/ CK slew rate >1.0V/ns.
20. Mi n(tCL, tCH) refers to thesmallerofthe actual clocklow timeand theactualclock high timeasprovidedtothe
device.
Ti ming patterns:
tCK= min,tRRD =2*tCK,B L= 4,tRCD=3*tCK ,R eadwith Autoprecharge
Read:A0N A1 R0 A2 R1 NR 3A0N A1 R 0–repeatthe same timing with randomaddresschanging
*100% of datachanging at everyburst
Legend:A =Activate,R= Read,P=Precharge,N =NOP
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