參數(shù)資料
型號: IS43R32800B-5BL
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 8M X 32 DDR DRAM, 0.7 ns, PBGA144
封裝: 12 X 12 MM, 0.80 MM PITCH, LEAD FREE, MINI, FBGA-144
文件頁數(shù): 15/39頁
文件大?。?/td> 507K
代理商: IS43R32800B-5BL
22
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00D
03/19/08
IS43R32800B
/CS
/RAS
/CAS
/WE
A11-A0
V
BA 0
BA 1
/CLK
CL K
BA 1B A0 A11A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
01
00
DS
DD
0Normal
1Weak
Drive
Strength
0DLL Enable
1DLL Disable
DL LD isable
EXTENDED MODE REGISTER
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional
functions include DLL enable/disable, output drive strength selection (optional). These functions are controlled via
the bits shown in Figure EXTENDED MODE REGISTER.
The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 1 and BA1 =
0) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode
Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the
specified time before initiating any subsequent operation. After tMRD from a MRS command the DDR SDRAM is
ready for a new command. Violating either of these requirements will result in unspecified operation.
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon
returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting
Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled a DLL Reset must follow and
200 clock cycles must occur before any executable command can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The ISSI DDR SDRAM also supports a
weak driver strength option, intended for lighter load and/or point-to-point environments.
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