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參數(shù)資料
| 型號(hào)： | IDT82P20516DBFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 42/115頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 16CH SH 484BGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 16 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 2.89W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 484-CABGA（19x19） |
| 包裝： | 托盤 |
| 包括： | AIS 警報(bào)檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠(yuǎn)程檢測器和發(fā)生器 |
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IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Functional Description
32
December 17, 2009
3.5.3
LOSS OF SIGNAL (LOS) DETECTION
The IDT82P20516 detects three kinds of LOS:
LLOS: Line LOS, detected in the receive path;
SLOS: System LOS, detected in the transmit system side;
TLOS: Transmit LOS, detected in the transmit line side.
3.5.3.1 Line LOS (LLOS)
The amplitude and density of the data received from the line side are
monitored. When the amplitude of the data is less than Q Vpp for N
consecutive pulse intervals, LLOS is declared. When the amplitude of
the data is more than P Vpp and the average density of marks is at least
12.5% for M consecutive pulse intervals starting with a mark, LLOS is
cleared. Here Q is defined by the ALOS[2:0] bits (b6~4, LOS,...). P is the
sum of Q and 250 mVpp. N and M are defined by the LAC bit (b7,
In E1 mode, LLOS detection supports G.775 and ETSI 300233/I.431.
The criteria are selected by the LAC bit (b7, LOS,...).
When LLOS is detected, the LLOS_S bit (b0, STAT0,...) will be set. A
transition from ‘0’ to ‘1’ on the LLOS_S bit (b0, STAT0,...) or any transi-
tion (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the LLOS_S bit (b0, STAT0,...) will
set the LLOS_IS bit (b0, INTS0,...) to ‘1’, as selected by the LOS_IES bit
(b1, INTES,...). When the LLOS_IS bit (b0, INTS0,...) is ‘1’, an interrupt
will be reported by INT if not masked by the LLOS_IM bit (b0, INTM0,...).
Two pins (LLOS0 and LLOS) are dedicated to LLOS indication.
Whether LLOS is detected in channel 0 or not, LLOS0 is high for a
CLKE1 clock cycle to indicate the start position on LLOS. LLOS indi-
cates LLOS status of all 16 channels in a serial format and repeats every
17 cycles. Refer to Figure-15. LLOS0 and LLOS are updated on the
rising edge of CLKE1. When the clock output on CLKE1 is disabled,
LLOS0 and LLOS will be held in High-Z state. The output on CLKE1 is
controlled by the CLKE1_EN bit (b3, CLKG) and the CLKE1 bit (b2,
CLKG). Refer to section 8.9 on page 105 for CLKE1 timing characteris-
tics.
LLOS may be counted by an internal Error Counte. Refer to
During LLOS, in Receive Single Rail NRZ Format mode, Receive
Dual Rail NRZ Format mode and Receive Dual Rail RZ Format mode,
RDPn/RDNn output low level. In Receive Dual Rail Sliced mode RDPn/
RDNn still output sliced data. RCLKn (if available) outputs high level or
During LLOS, if any of AIS, pattern generation in the receive path or
Digital Loopback is enabled or automatic digital loopback happens,
RDPn/RDNn and RCLKn output corresponding data and clock, and the
setting of the RCKH bit (b7, RCF0,...) is ignored. Refer to the corre-
sponding chapters for details.
Figure-15 LLOS Indication on Pins
1. XCLK is derived from MCLK. It is 2.048 MHz in E1 mode.
Table-10 LLOS Criteria
Operation
Mode
LAC
Criteria
LLOS Declaring
LLOS Clearing
E1
0
G.775
below Q Vpp, N = 32 bits
above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
1
ETSI 300233/
I.431
below Q Vpp, N = 2048 bits
above P Vpp, 12.5% mark density with less than 16 consecutive zeros, M = 32 bits
One LLOS Indication Cycle
LLOS
LLOS0
CLKE1
CH0 CH1
CH14 CH15
01
2
314
15
0
CH0
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| IDT82P20516DBFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
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