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參數(shù)資料
| 型號： | IDT82P20516DBFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 33/115頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 16CH SH 484BGA |
| 標(biāo)準(zhǔn)包裝： | 84 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 16 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 2.89W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 484-CABGA（19x19） |
| 包裝： | 托盤 |
| 包括： | AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠(yuǎn)程檢測器和發(fā)生器 |
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IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Functional Description
24
December 17, 2009
3.3.2
TX CLOCK RECOVERY
The Tx Clock Recovery is used only when the transmit system inter-
face is in Dual Rail RZ Format mode. When the transmit system inter-
face is in other modes, the Tx Clock Recovery is bypassed
automatically.
The Tx Clock Recovery is used to recover the clock signal from the
data input on TDPn and TDNn.
3.3.3
ENCODER
The Encoder is used only when the transmit system interface is in
Single Rail NRZ Format mode. When the transmit system interface is in
other modes, the Encoder is bypassed automatically.
In E1 mode, the data to be transmitted is encoded by AMI or HDB3
line code rule. The line code rule is selected by the T_CODE bit (b2,
3.3.4
WAVEFORM SHAPER
The IDT82P20516 provides two ways to manipulate the pulse shape
before data is transmitted:
Preset Waveform Template;
User-Programmable Arbitrary Waveform.
3.3.4.1 Preset Waveform Template
In E1 applications, the waveform template meets G.703, as shown in
Figure-9. It is measured in the near end line side, as shown in Figure-10.
In E1 applications, the PULS[3:0] should be set to ‘0000’ if differential
signals (output from TTIP and TRING) are coupled to a 75
coaxial
cable using Internal Impedance matching mode; the PULS[3:0] should
be set to ‘0001’ for other E1 interfaces. Refer to Table-5 for details.
Figure-9 E1 Waveform Template
Figure-10 E1 Waveform Template Measurement Circuit
Table-4 Multiplex Pin Used in Transmit System Interface
Transmit System
Interface
Multiplex Pin Used On Transmit System
Interface
TDn / TDPn
TDNn
TCLKn / TDNn
Single Rail NRZ Format
TDn 1
TCLKn 2
Dual Rail NRZ Format
TDPn 1
TDNn 1
TCLKn 2
Dual Rail RZ Format
TDPn 1
TDNn 1
Note:
1. The active level on TDn, TDPn and TDNn is selected by the TD_INV bit (b3,
2. The active edge of TCLKn is selected by the TCK_ES bit (b4, TCF1,...). If TCLKn is
missing, i.e., no transition for more than 64 E1 clock cycles, the TCKLOS_S bit (b3,
STAT0,...) will be set. A transition from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) or
any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TCKLOS_S bit (b3, STAT0,...) will
set the TCKLOS_IS bit (b3, INTS0,...) to ‘1’, as selected by the TCKLOS_IES bit (b3,
INTES,...). When the TCKLOS_IS bit (b3, INTS0,...) is ‘1’, an interrupt will be reported
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Normalized
A
m
plitude
Time in Unit Intervals
IDT82P20516
VOUT
RLOAD
TTIPn
TRINGn
Note: RLOAD = 75
or 120 (+ 5%)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P20516DBFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P20516DBFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
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