參數(shù)資料
型號: IDT82P20516DBFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 32/115頁
文件大小: 0K
描述: IC LIU T1/E1/J1 16CH SH 484BGA
標準包裝: 84
功能: 線路接口單元(LIU)
接口: E1,J1,T1
電路數(shù): 16
電源電壓: 1.8V, 3.3V
功率(瓦特): 2.89W
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-LFBGA
供應(yīng)商設(shè)備封裝: 484-CABGA(19x19)
包裝: 托盤
包括: AIS 警報檢測器和發(fā)生器,回送功能,PRBS 發(fā)生器 / 檢測器,遠程檢測器和發(fā)生器
IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Functional Description
23
December 17, 2009
3.2.7
RECEIVER POWER DOWN
Set the R_OFF bit (b5, RCF0,...) to ‘1’ will power down the corre-
sponding receiver.
In this way, the corresponding receive circuit is turned off and the
RTIPn/RRINGn pins are forced to High-Z state. The pins on receive
system interface (including RDn/RDPn, RDNn, RCLKn) will be in High-Z
state if the RHZ bit (b6, RCF0,...) is ‘1’ or in low level if the RHZ bit (b6,
RCF0,...) is ‘0’.
After clearing the R_OFF bit (b5, RCF0,...), it will take 1 ms for the
receiver to achieve steady state, i.e., to return to the previous configura-
tion and performance.
3.3
TRANSMIT PATH
3.3.1
TRANSMIT SYSTEM INTERFACE
The data from the system side is input to the device in three modes:
Single Rail NRZ Format mode, Dual Rail NRZ Format mode and Dual
Rail RZ Format mode, as selected by the T_MD[1:0] bits (b1~0,
If data is input on TDn in NRZ format and a 2.048 MHz (in E1 mode)
clock is input on TCLKn, the transmit system interface is in Single Rail
NRZ Format mode. In this mode, the data is encoded and sampled on
the active edge of TCLKn.
If data is input on TDPn and TDNn in NRZ format and a 2.048 MHz
(in E1 mode) clock is input on TCLKn, the transmit system interface is in
Dual Rail NRZ Format mode. In this mode, the data is pre-encoded and
sampled on the active edge of TCLKn.
If data is input on TDPn and TDNn in RZ format and no transmit
clock is input, the transmit system interface is in Dual Rail RZ Format
mode. In this mode, the data is pre-encoded.
Table-4 summarizes the multiplex pin used in different transmit
system interface.
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