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參數(shù)資料
| 型號： | IDT82P20516DBFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 22/115頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 16CH SH 484BGA |
| 標準包裝： | 84 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 16 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 2.89W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 484-LFBGA |
| 供應商設備封裝： | 484-CABGA（19x19） |
| 包裝： | 托盤 |
| 包括： | AIS 警報檢測器和發(fā)生器，回送功能，PRBS 發(fā)生器 / 檢測器，遠程檢測器和發(fā)生器 |
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IDT82P20516
16-CHANNEL SHORT HAUL E1 LINE INTERFACE UNIT
Pin Description
14
December 17, 2009
LLOS0
Output
AA13
LLOS0: Receive Line Loss Of Signal for Start Position
LLOS0 can indicate the start position on the LLOS pin.
When the clock output on CLKE1 is enabled, LLOS0 pulses high for one CLKE1 clock cycle to
indicate the start position on the LLOS pin. When CLKE1 outputs 8 KHz clock, LLOS0 pulses
high for one 8 KHz clock cycle (125 s) every seventeen 8 KHz clock cycles; when CLKE1
outputs 2.048 MHz clock, LLOS0 pulses high for one 2.048 MHz clock cycle (488 ns) every
seventeen 2.048 MHz clock cycles. LLOS0 is updated on the rising edge of CLKE1.
When the clock output on CLKE1 is disabled, LLOS0 will be held in High-Z state.
(Refer to Section 3.5.3.1 Line LOS (LLOS) for details.)
TDn / TDPn
(n=0~15)
Input
AB5, V4, W6, AA4, AA6, AA16,
V19, V17, D18, B17, B15, B13,
B10, B8, B16, C5
TDn: Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Single Rail NRZ Format mode, this multi-
plex pin is used as TDn.
TDn accepts Single Rail NRZ data. The data is sampled into the device on the active edge of
TCLKn.
The active level on TDn is selected by the TD_INV bit (b3, TCF1,...).
TDPn: Positive Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Dual Rail NRZ Format mode or Dual Rail
RZ Format mode, this multiplex pin is used as TDPn.
In Transmit Dual Rail NRZ Format mode, the pre-encoded NRZ data is input on TDPn and
TDNn and sampled on the active edge of TCLKn.
In Transmit Dual Rail RZ Format mode, the pre-encoded RZ data is input on TDPn and TDNn.
The line code is as follows (when the TD_INV bit (b3, TCF1,...) is ‘0’):
The active level on TDPn and TDNn is selected by the TD_INV bit (b3, TCF1,...).
TDNn
(n=0~15)
Input / Output
AB6, Y3, W5, AB1, AB3, AB19,
AB21, AA19, C18, A17, A15, A13,
A10, A8, A6, D5
TDNn: Negative Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Dual Rail NRZ Format mode, this multi-
plex pin is used as TDNn.
(Refer to the description of TDPn for details).
TCLKn / TDNn
(n=0~15)
Input
W10, W3, V6, V7, V8, W17, V16,
AA20, E18, D16, D14, D12, D11,
D9, D7, B5
TCLKn: Transmit Clock for Channel 0 ~ 15
When the transmit system interface is configured to Single Rail NRZ Format mode or Dual
Rail NRZ Format mode, this multiplex pin is used as TCLKn.
TCLKn inputs a 2.048 MHz (in E1 mode) clock.
The data input on TDn (in Transmit Single Rail NRZ Format mode) or TDPn/TDNn (in Trans-
mit Dual Rail NRZ Format mode) is sampled on the active edge of TCLKn.
TDNn: Negative Transmit Data for Channel 0 ~ 15
When the transmit system interface is configured to Dual Rail RZ Format mode, this multiplex
pin is used as TDNn.
(Refer to the description of TDPn for details).
Name
I / O
Pin No.
Description
TDPn
TDNn
Output Pulse on TTIPn Output Pulse on TRINGn *
0
Space
0
1
Negative Pulse
Positive Pulse
1
0
Positive Pulse
Negative Pulse
1
Space
Note:
* For Transmit Single Ended line interface, TRINGn should be open.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P20516DBFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P20516DBFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel Short Haul E1 Line Interface Unit |
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