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| 型號： | IBMN364164CT3C-68 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 9/71頁 |
| 文件大?。?/td> | 1251K |
| 代理商： | IBMN364164CT3C-68 |
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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 71
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling
RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the
rising edge of the clock. The bank select address A12 - A13 is used to select the desired bank. The row
address A0 - A11 is used to determine which row to activate in the selected bank.
The Bank Activate command must be applied before any Read or Write operation can be executed. The
delay from when the Bank Activate command is applied to when the first read or write operation can begin
must meet or exceed the RAS to CAS delay time (t
RCD
). Once a bank has been activated it must be pre-
charged before another Bank Activate command can be applied to the same bank. The minimum time inter-
val between successive Bank Activate commands to the same bank is determined by the RAS cycle time of
the device (t
RC
). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B
and vice versa) is the Bank to Bank delay time (t
RRD
). The maximum time that each bank can be held active
is specified as t
RAS(max)
.
Bank Select
The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge,
Read, or Write operation.
Bank Activate Command Cycle
Bank Selection Bits
BS0
BS1
Bank
0
0
Bank 0
0
1
Bank 1
1
0
Bank 2
1
1
Bank 3
ADDRESS
CLK
T0
T2
T1
T3
Tn
Tn+1
Tn+2
Tn+3
COMMAND
NOP
NOP
NOP
NOP
Bank A
Row Addr.
Bank A
Activate
PWrite A
Bank A
Col. Addr.
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
Bank B
Activate
Bank A
Row Addr.
Bank A
Activate
RAS-CAS delay (
t
RCD
)
: “H” or “L”
RAS Cycle time (
t
RC
)
RAS - RAS delay time (
t
RRD
)
Bank B
Row Addr.
(CAS Latency = 3, t
RCD
= 3)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBMN364164CT3C-75A | x16 SDRAM |
| IBMN364404CT3C-260 | x4 SDRAM |
| IBMN364404CT3C-360 | x4 SDRAM |
| IBMN364404CT3C-75A | x4 SDRAM |
| IBMN364804CT3C-260 | x8 SDRAM |
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