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參數資料
| 型號： | IBMN364164CT3C-68 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內存 |
| 文件頁數： | 11/71頁 |
| 文件大小： | 1251K |
| 代理商： | IBMN364164CT3C-68 |
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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 71
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register
sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the
start of the command to when the data from the first cell appears on the outputs is equal to the value of the
CAS latency that is set in the Mode Register.
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read Command continues to appear on the outputs until the CAS latency from
the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command
appears.
Burst Read Operation
COMMAND
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DOUT A
0
CAS latency = 2
t
CK2,
DQs
t
CK3,
DQs
CAS latency = 3
DOUT A
1
DOUT A
2
DOUT A
3
NOP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A
0
DOUT A
1
DOUT A
2
DOUT A
3
(Burst Length = 4, CAS latency = 2, 3)
相關PDF資料 |
PDF描述 |
|---|---|
| IBMN364164CT3C-75A | x16 SDRAM |
| IBMN364404CT3C-260 | x4 SDRAM |
| IBMN364404CT3C-360 | x4 SDRAM |
| IBMN364404CT3C-75A | x4 SDRAM |
| IBMN364804CT3C-260 | x8 SDRAM |
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