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| 型號(hào)： | IBMN364164CT3C-68 |
| 英文描述： | x16 SDRAM |
| 中文描述： | x16內(nèi)存 |
| 文件頁數(shù)： | 19/71頁 |
| 文件大小： | 1251K |
| 代理商： | IBMN364164CT3C-68 |
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IBMN364164
IBMN364404
IBMN364804
64Mb Synchronous DRAM - Die Revision C
19L3265.E35856B
1/01
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 19 of 71
Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Pre-
charge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM,
the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically
begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the
Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank
remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is
issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute
as normal with the exception that the active bank will begin to precharge before all burst read cycles have
been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last
data output. Auto-precharge can also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. How-
ever, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank.
Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write
cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has
started the bank cannot be reactivated until the Precharge time (t
RP
) has been satisfied. It should be noted
that the device will not respond to the Auto-Precharge command if the device is programmed for full page
burst read or write cycles, or full page burst read cycles with single write operation.
When using the Auto-precharge Command, the interval between the Bank Activate Command and the begin-
ning of the internal precharge operation must satisfy t
RAS
(min). If this interval does not satisfy t
RAS
(min) then
t
RCD
must be extended.
Burst Read with Auto-Precharge
COMMAND
NOP
NOP
NOP
NOP
READ A
Auto-Precharge
t
RP
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
t
RP
*
*
*
t
RP
is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
t
CK2,
DQs
CAS latency = 2
t
CK3,
DQs
CAS latency = 3
Begin Auto-precharge
Bank can be reactivated at completion of t
RP
.
DOUT A
0
DOUT A
0
NOP
(Burst Length = 1, CAS Latency = 2, 3)
相關(guān)PDF資料 |
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| IBMN364164CT3C-75A | x16 SDRAM |
| IBMN364404CT3C-260 | x4 SDRAM |
| IBMN364404CT3C-360 | x4 SDRAM |
| IBMN364404CT3C-75A | x4 SDRAM |
| IBMN364804CT3C-260 | x8 SDRAM |
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