參數(shù)資料
型號(hào): IBMN364164CT3C-68
英文描述: x16 SDRAM
中文描述: x16內(nèi)存
文件頁(yè)數(shù): 16/71頁(yè)
文件大?。?/td> 1251K
代理商: IBMN364164CT3C-68
IBMN364164
IBMN364404
64Mb Synchronous DRAM - Die Revision C
IBMN364804
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 71
19L3265.E35856B
1/01
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is
registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data
appears on the outputs to avoid data contention. When the Read Command is registered, any residual data
from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is
initiated will actually be written to the memory.
Minimum Write to Read Interval
COMMAND
NOP
WRITE A
READ B
NOP
NOP
NOP
NOP
NOP
NOP
t
CK2,
DQs
CAS latency = 2
DIN A
0
t
CK3,
DQs
CAS latency = 3
DIN A
0
CLK
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
DOUT B
0
DOUT B
1
DOUT B
2
DOUT B
3
(Burst Length = 4, CAS latency = 2, 3)
: “H” or “L”
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PDF描述
IBMN364164CT3C-75A x16 SDRAM
IBMN364404CT3C-260 x4 SDRAM
IBMN364404CT3C-360 x4 SDRAM
IBMN364404CT3C-75A x4 SDRAM
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