參數(shù)資料
型號(hào)： HB52R329E22
廠商： Hitachi,Ltd.
英文描述： 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM)
中文描述： 注冊(cè)使用256 MB SDRAM的內(nèi)存（256 MB的寄存同步的DRAM內(nèi)存）
文件頁(yè)數(shù)： 54/67頁(yè)
文件大?。?/td> 630K
代理商： HB52R329E22
HB52R329E22-D
54
Refresh
Auto-refresh:
All the banks must be precharged before executing an auto-refresh command. Since the
auto-refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not
required.
Self-refresh:
After executing a self-refresh command, the self-refresh operation continues while CKE is
held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-
refresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6
μ
s after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6
μ
s after
exiting from self-refresh mode.
Others
Power-down mode:
The SDRAM module enters power-down mode when CKE goes Low in the IDLE
state. In power down mode, power consumption is suppressed by deactivating the input initial circuit.
Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM
module exits from the power down mode, and command input is enabled from the next clock. In this
mode, internal refresh is not performed.
Clock suspend mode:
By driving CKE to Low during a bank-active or read/write operation, the SDRAM
module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the SDRAM module terminates clock suspend
mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence:
The SDRAM module should be gone on
the following sequence with power up.
The CK, CKE,
S
, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100
μ
s after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has V
CC
clamp diodes for CK, CKE,
S
, DQMB and DQ pins. If these pins go high
before power up, the large current flows from these pins to V
CC
through the diodes.
Initialization sequence:
When 200
μ
s or more has past after the above power-up sequence, all banks must
be precharged using the precharge command (PALL). After t
RP
delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQM, DQMU/DQML to High, the output buffer becomes High-Z during Initialization sequence,
to avoid DQ bus contention on memory system formed with a number of device.
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HB52R329E22-A6F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module
HB52R329E22-B6F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module
HB52R329E22-F 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM
HB52R329E2-B6 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module
HB52R649E1U-A6B 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM
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