參數(shù)資料
型號(hào): HB52RD328DC
廠商: Hitachi,Ltd.
英文描述: 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM)
中文描述: 256 MB的無(wú)緩沖內(nèi)存的SODIMM(256 MB的未緩沖同步內(nèi)存的SODIMM)
文件頁(yè)數(shù): 1/68頁(yè)
文件大?。?/td> 885K
代理商: HB52RD328DC
HB52RD328DC-F
256 MB Unbuffered SDRAM S.O.DIMM
32-Mword
×
64-bit, 100 MHz Memory Bus, 2-Bank Module
(32 pcs of 16 M
×
4 components)
PC100 SDRAM
ADE-203-1044B (Z)
Rev. 1.0
Jan. 18, 2000
Description
The HB52RD328DC is a 16M
×
64
×
2 banks Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 32 pieces of 64-Mbit SDRAM (HM5264405FTB) sealed in TCP
package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the
product is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density
mounting possible without surface mount technology. It provides common data inputs and outputs.
Decoupling capacitors are mounted beside TCP on the module board.
Note:
Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM
144-pin Zig Zag Dual tabs socket type (dual lead out)
Outline: 67.60 mm (Length)
×
31.75 mm (Height)
×
3.80 mm (Thickness)
Lead pitch: 0.80 mm
3.3 V power supply
Clock frequency: 100 MHz (max)
LVTTL interface
Data bus width:
×
64 Non parity
Single pulsed
RAS
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length : 1/2/4/8/full page
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