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參數(shù)資料
| 型號： | HB52R329E22 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM) |
| 中文描述： | 注冊使用256 MB SDRAM的內存（256 MB的寄存同步的DRAM內存） |
| 文件頁數(shù)： | 35/67頁 |
| 文件大?。?/td> | 630K |
| 代理商： | HB52R329E22 |
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HB52R329E22-D
35
Operation of the Registered SDRAM module
Read/Write Operations
Bank active:
Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according
to the status of the Bank select address (BA) pin, and the row address (AX0 to AX11) is activated by the
A0 to A11 pins at the bank active command cycle. An interval of t
RCD
is required between the bank active
command input and the following read/write command input.
Read operation:
A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (
CE
Latency - 1) cycle after read command set. The SDRAM module can perform a burst read
operation.
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the
column address and the bank select address (BA) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the
CE
Latency. The
CE
Latency can be set to 3 or 4.
When the burst length is 1, 2, 4 or 8, the Dout buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output.
The
CE
latency and burst length must be specified at the mode register.
CE
Latency
READ
CK
Command
Dout
ACTV
Row
Column
Address
CL = 3
CL = 4
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
t
RCD
CL =
CE
latency
Burst Length = 4
相關PDF資料 |
PDF描述 |
|---|---|
| HB52R329E2 | 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM) |
| HB52RD168DB | 128 MB Unbuffered SDRAM S.O.DIMM(128MB 未緩沖同步DRAM DIMM) |
| HB52RD328DC | 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM) |
| HB52RF1289E2-75B | x72 SDRAM Module |
| HB52RF1289E2 | 1 GB Registered SDRAM DIMM 128-Mword 】 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M 】 4 Components) PC133 SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HB52R329E22-A6F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HB52R329E22-B6F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HB52R329E22-F | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256 MB Registered SDRAM DIMM 32-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module (36 pcs of 16 M × 4 Components) PC100 SDRAM |
| HB52R329E2-B6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HB52R649E1U-A6B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 100 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC100 SDRAM |
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