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參數(shù)資料
| 型號(hào)： | GS8180D18 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| 中文描述： | 1兆x 18位獨(dú)立的I / O西格瑪?shù)腄DR SRAM的（100萬(wàn)× 18位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM） |
| 文件頁(yè)數(shù)： | 6/33頁(yè) |
| 文件大?。?/td> | 874K |
| 代理商： | GS8180D18 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
6/33
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180D09/18B-333/300/275/250
Background
Separate I/O Sigma RAMs have been designed to be closely related to Common I/O Sigma RAMs in pinout and overall
architecture. The similarities give Separate I/O Sigma RAMs a cost advantage by allowing users and vendors to reuse supporting
infrastructure and design elements. Separate I/O Sigma RAMs come in Single and Double Data Rate configurations. Because they
are designed to operate with both the input data pins and the output data pins operating at full speed all the time, Separate I/O
Sigma RAMs produce twice the bandwidth of Common I/O SRAMs of the same speed and output bus width.
B4, B9, C3, D4, D5, D7,
D8, K4, K8, K9, T4, T5,
T7, T8, U3, U5, U7, U9
A10, A11, B8, B10, B11,
C4, C10, C11, D10, D11,
E10, E11, F10, F11,
G10, G11, H10, H11,
J10, J11, L1, L2, M1, M2,
N1, N2, P1, P2, R1, R2,
T1, T2, U1, U2, V1, V2,
W1, W2
NC
No Connect
—
Not connected to die or any other pin
(all versions)
NC
No Connect
—
Not connected to die or any other pin
(x09 and x18 versions)
C5, C8
NC
No Connect
—
Not connected to die or any other pin
(x18 and x36 versions)
B3, C9, K10, K11, L10,
L11, M10, M11, N10,
N11, P10, P11, R10,
R11, T10, T11, U10,
U11, V10, V11, W10,
W11
NC
No Connect
—
Not connected to die or any other pin
(x18 version only)
C7
NC
No Connect
—
Not connected to die or any other pin
(x36 version only)
Active Low
B6
W
Write
Input
E5, E6, E7, G5, G7, J5,
J7, L5, L7, N5, N7, R5,
R6, R7
E3, E4, E8, E9, G3, G4,
G8, G9, J3, J4, J8, J9,
L3, L4, L8, L9, N3, N4,
N8, N9, R3, R4, R8, R9
D3, D9, F3, F4, F5, F7,
F8, F9, H3, H4, H5, H7,
H8, H9, K5, K7, M3, M4,
M5, M7, M8, M9, P3, P4,
P5, P7, P8, P9, T3, T9
F6
V
DD
Core Power Supply
Input
1.8 V Nominal
V
DDQ
Output Driver Power Supply
Input
1.8 V or 1.5 V Nominal
V
SS
Ground
Input
—
ZQ
Output Impedance Control
Input
—
Pin Description Table
Pin Location
Symbol
Description
Type
Comments
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8180S36 | 512K x 36Bit Separate I/O Sigma DDR SRAM(512K x 36位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S18 | 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS8180S09 | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| GS820322T-138 | 64K x 32 2M Synchronous Burst SRAM |
| GS82032Q-100 | 64K x 32 2M Synchronous Burst SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8180Q36D-167X | 制造商:GSI Technology 功能描述:512K X 36 (18 MEG)SIGMA QUAD I -SEPERATE I/O BURST OF 2 - Trays |
| GS8180QV36BGD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 512KX36 2.5NS 165FPBGA - Trays |
| GS8180QV36BGD-167I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 512KX36 2.5NS 165FPBGA - Trays |
| GS8182D08BD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.5NS 165FPBGA - Trays |
| GS8182D08BD-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays |
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