參數(shù)資料
型號: GS8180D18
廠商: GSI TECHNOLOGY
英文描述: 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述: 1兆x 18位獨(dú)立的I / O西格瑪?shù)腄DR SRAM的(100萬× 18位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
文件頁數(shù): 28/33頁
文件大小: 874K
代理商: GS8180D18
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
28/33
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180D09/18B-333/300/275/250
JTAG Port Recommended Operating Conditions and DC Characteristics
JTAG Port AC Test Conditions
Parameter
Symbol
V
IHT
V
ILT
I
INTH
I
INTL
I
OLT
V
OHT
V
OLT
Min.
0.65 * V
DD
Max.
V
DD
+0.3
0.35 * V
DD
Unit
Notes
Test Port Input High Voltage
V
1
Test Port Input Low Voltage
–0.3
V
1
TMS, TCK and TDI Input Leakage Current
–100
2
uA
2
TMS, TCK and TDI Input Leakage Current
–2
2
uA
3
TDO Output Leakage Current
–2
2
uA
4
Test Port Output High Voltage
V
DDQ
– 100 mV
V
5, 6
Test Port Output Low Voltage
100 mV
V
7
Notes:
1.
2.
3.
4.
5.
6.
7.
Input Under/overshoot voltage must be –1 V < Vi < V
DD
+ 1 V with a pulse width not to exceed 20% tTKC.
V
DD
V
IN
V
IL
0 V
V
IN
V
IL
Output Disable, V
OUT
= 0 to V
DD
The TDO output driver is served by the V
DD
supply.
I
OH
= –100 uA
I
OL
= +100 uA
Notes:
1.
2.
Include scope and jig capacitance.
Test conditions as as shown unless otherwise noted.
Parameter
Conditions
V
DD
– 200 mV
200 mV
1 V/ns
V
DD
/2
V
DD
/2
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
DQ
V
T
= V
DD
/2
50
JTAG Port AC Test Load
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