參數(shù)資料
型號(hào)： GS8180D18
廠商： GSI TECHNOLOGY
英文描述： 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述： 1兆x 18位獨(dú)立的I / O西格瑪?shù)腄DR SRAM的（100萬(wàn)× 18位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM）
文件頁(yè)數(shù)： 12/33頁(yè)
文件大小： 874K
代理商： GS8180D18
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
12/33
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180D09/18B-333/300/275/250
Echo Clock Control in Two Banks of Separate I/O DDR Sigma RAMs
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
In some applications it may be appropriate to pause between banks—to deselect both RAMs with E1 before resuming read
operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a Write to Bank 2
would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
DC0
DC1
DC2
DC3
DE0
DE1
DE2
DE3
QD0
QD1
QD2
QD3
QB0
QB1
QB2
QB3
QB0
QB1
QB2
QB3
QD0
QD1
QD2
QD3
Note:
1 E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
2 Reads or Writes launched in a bank continue in the same bank.
CQ
Bank 1
CQ
Bank 2
CQ1 + CQ2
Q Bank 1 +
Q Bank 2
D
Bank 2
/E2 Bank 1
E2 Bank 2
Q
Bank 1
Q
Bank 2
G
/E
1
/W
D
Bank 1
C
D
E
F
CK
Address
XX
B
Write
Bank 2
Read
Bank 1
Write
Bank 1
-
Bank 2
Bank 2
Bank 1
No Op
Read
Write
Read
相關(guān)PDF資料
PDF描述
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GS8180S18 1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
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