參數(shù)資料
型號(hào)： EVAL-ADUC834QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 59/80頁(yè)
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC834
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC834
所含物品： 評(píng)估板，線纜，電源，軟件和文檔
REV. A
–62–
ADuC834
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each inter-
rupt. An interrupt of a high priority may interrupt the service
routine of a low priority interrupt, and if two interrupts of different
priority occur at the same time, the higher level interrupt will be
serviced first. An interrupt cannot be interrupted by another
interrupt of the same priority level. If two interrupts of the same
priority level occur simultaneously, a polling sequence is used to
determine which interrupt is serviced first. The polling sequence
is shown in Table XXXVIII.
Table XXXVIII. Priority within an Interrupt Level
Source
Priority
Description
PSMI
1 (Highest)
Power Supply Monitor Interrupt
WDS
2
Watchdog Interrupt
IE0
3
External Interrupt 0
RDY0/RDY1
4
ADC Interrupt
TF0
5
Timer/Counter 0 Interrupt
IE1
6
External Interrupt 1
TF1
7
Timer/Counter 1 Interrupt
ISPI/I2CI
8
SPI Interrupt
RI + TI
9
Serial Interrupt
TF2 + EXF2
10
Timer/Counter 2 Interrupt
TII
11 (Lowest)
Time Interval Counter Interrupt
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table XXXIX.
Table XXXIX. Interrupt Vector Addresses
Source
Vector Address
IE0
0003H
TF0
000BH
IE1
0013H
TF1
001BH
RI + TI
0023H
TF2 + EXF2
002BH
RDY0/RDY1 (ADC)
0033H
ISPI/I2CI
003BH
PSMI
0043H
TII
0053H
WDS (WDIR = 1)
*
005BH
*The watchdog can be configured to generate an interrupt instead of a reset
when it times out. This is used for logging errors or to examine the internal
status of the microcontroller core to understand, from a software debug point
of view, why a watchdog timeout occurred. The watchdog interrupt is slightly
different from the normal interrupts in that its priority level is always set to 1
and it is not possible to disable the interrupt via the global disable bit (
EA) in
the IE SFR. This is done to ensure that the interrupt will always be responded
to if a watchdog timeout occurs. The watchdog will only produce an interrupt
if the watchdog timeout is greater than zero.
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