參數(shù)資料
型號(hào)： EVAL-ADUC834QSZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/80頁
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC834
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC834
所含物品： 評(píng)估板，線纜，電源，軟件和文檔
REV. A
–38–
ADuC834
Mode 4: Dual NRZ 16-Bit
-
DAC
Mode 4 provides a high speed PWM output similar to that of a
Σ- DAC. Typically, this mode will be used with the PWM
clock equal to 12.58 MHz.
In this mode, P1.0 and P1.1 are updated every PWM clock
(80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit
PWM) PWM0 (P1.0) is high for PWM0H/L cycles and low for
(65536 – PWM0H/L) cycles. Similarly PWM1 (P1.1) is high for
PWM1H/L cycles and low for (65536 – PWM1H/L) cycles.
If PWM1H is set to 4010H (slightly above one quarter of FS),
then typically P1.1 will be low for three clocks and high for one
clock (each clock is approximately 80 ns). Over every 65536
clocks, the PWM will compromise for the fact that the output
should be slightly above one quarter of full scale by having a
high cycle followed by only two low cycles.
12.583MHz
16-BIT
80 s
0
16-BIT
CARRY OUT AT P1.0
CARRY OUT AT P1.1
PWM0H/L = C000H
PWM1H/L = 4000H
00
1
00
0
LATCH
0
11
1
0
Figure 30. PWM Mode 4
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required with a 1 in the LSB position. If, for
example, only 12-bit performance is required, write “0001” to
the 4 LSBs. This means that a 12-bit accurate
Σ- DAC output
can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs
gives an 8-bit accurate
Σ- DAC output at 49 kHz.
Mode 5: Dual 8-Bit PWM
In Mode 5, the duty cycle of the PWM outputs and the resolu-
tion of the PWM outputs are individually programmable. The
maximum resolution of the PWM output is eight bits.
The output resolution is set by the PWM1L and PWM1H SFRs
for the P1.0 and P1.1 outputs respectively. PWM0L and
PWM0H sets the duty cycles of the PWM outputs at P1.0 and
P1.1, respectively. Both PWMs have the same clock source and
clock divider.
P1.1
P1.0
PWM COUNTERS
PWM1H
0
PWM1L
PWM0H
PWM0L
Figure 31. PWM Mode 5
Mode 6: Dual RZ 16-Bit
-
DAC
Mode 6 provides a high speed PWM output similar to that of a
Σ- DAC. Mode 6 operates very similarly to Mode 4. However,
the key difference is that Mode 6 provides return to zero (RZ)
Σ- DAC output. Mode 4 provides non-return-to-zero Σ- DAC
outputs. The RZ mode ensures that any difference in the rise
and fall times will not affect the
Σ- DAC INL. However, the
RZ mode halves the dynamic range of the
Σ- DAC outputs from
0
→AV
DD to 0
→AV
DD/2. For best results, this mode should be
used with a PWM clock divider of 4.
If PWM1H is set to 4010H (slightly above one quarter of FS)
then typically P1.1 will be low for three full clocks (3
80 ns),
high for half a clock (40 ns) and then low again for half a clock
(40 ns) before repeating itself. Over every 65536 clocks, the
PWM will compromise for the fact that the output should be
slightly above one quarter of full scale by leaving the output
high for two half clocks in four every so often.
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required with a 1 in the LSB position. If, for
example, only 12-bit performance is required, write “0001” to
the 4 LSBs. This means that a 12-bit accurate
Σ- DAC output
can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs
gives an 8-bit accurate
Σ- DAC output at 49 kHz.
3.146MHz
16-BIT
318 s
0
16-BIT
CARRY OUT AT P1.0
CARRY OUT AT P1.1
PWM0H/L = C000H
PWM1H/L = 4000H
00
1
00
0
LATCH
0
11
1
0
318 s
Figure 32. PWM Mode 6
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