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參數(shù)資料
| 型號(hào)： | EVAL-ADUC834QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/80頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV QUICK START ADUC834 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC834 |
| 所含物品： | 評(píng)估板，線纜，電源，軟件和文檔 |
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REV. A
ADuC834
–35–
Note that Figure 22 represents a transfer function in 0-to-VDD
mode only. In 0-to-VREF mode (with VREF < VDD), the lower
nonlinearity would be similar, but the upper portion of the
transfer function would follow the “ideal” line right to the end,
showing no signs of endpoint linearity errors.
VDD
VDD–50mV
VDD–100mV
100mV
50mV
0mV
000 Hex
FFF Hex
Figure 22. Endpoint Nonlinearities Due to Amplifier
Saturation
The endpoint nonlinearities conceptually illustrated in Figure 22
get worse as a function of output loading. Most of the ADuC834
data sheet specifications assume a 10 k
resistive load to
ground at the DAC output. As the output is forced to source or
sink more current, the nonlinear regions at the top or bottom
(respectively) of Figure 22 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figures 23 and 24 illustrate this behavior. It should be noted
that the upper trace in each of these figures is only valid for an
output range selection of 0-to-AVDD. In 0-to-VREF mode, DAC
loading will not cause high-side voltage drops as long as the
reference voltage remains below the upper trace in the corre-
sponding figure. For example, if AVDD = 3 V and VREF = 2.5 V,
the high-side voltage will not be affected by loads less than 5 mA.
But somewhere around 7 mA, the upper curve in Figure 24
drops below 2.5 V (VREF) indicating that at these higher currents,
the output will not be capable of reaching VREF.
SOURCE/SINK CURRENT – mA
5
05
10
15
OUTPUT
VOLTAGE
–
V
4
3
2
1
0
DAC LOADED WITH 0000 HEX
DAC LOADED WITH 0FFF HEX
Figure 23. Source and Sink Current Capability
with VREF = AVDD = 5 V
SOURCE/SINK CURRENT – mA
4
05
10
15
OUTPUT
VOLTAGE
–
V
3
1
0
DAC LOADED WITH 0000 HEX
DAC LOADED WITH 0FFF HEX
Figure 24. Source and Sink Current Capability
with VREF = VDD = 3 V
For larger loads, the current drive capability may not be
sufficient. In order to increase the source and sink current
capability of the DAC, an external buffer should be added, as
shown in Figure 25.
ADuC834
12
Figure 25. Buffering the DAC Output
The DAC output buffer also features a high impedance disable
function. In the chip’s default power-on state, the DAC is
disabled and its output is in a high impedance state (or “three-
state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, a pull-down resistor must be
added to each DAC output. Assuming this resistor is in place,
the DAC output will remain at ground potential whenever the
DAC is disabled.
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| EVAL-ADUC836QS | 制造商:Analog Devices 功能描述:MCU 8BIT 8052 CISC 62KB+4KB FLASH 3.6V 48LQFP - Bulk 制造商:Analog Devices 功能描述:KIT- ADUC836 DEV SYSTEM |
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| EVAL-ADUC841QSPZ | 功能描述:KIT DEV QUICK START ADUC841 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| EVAL-ADUC841QSPZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
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