- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄17112 > EVAL-ADUC834QSZ (Analog Devices Inc)KIT DEV QUICK START ADUC834 PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADUC834QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 28/80頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV QUICK START ADUC834 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC834 |
| 所含物品： | 評(píng)估板，線纜，電源，軟件和文檔 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)
REV. A
–34–
ADuC834
DAC
The ADuC834 incorporates a 12-bit, voltage output DAC
on-chip. It has a rail-to-rail voltage output buffer capable of driving
10 k
/100 pF. It has two selectable ranges, 0 V to VREF (the inter-
nal bandgap 2.5 V reference) and 0 V to AVDD. It can operate in
12-bit or 8-bit mode. The DAC has a control register, DACCON,
and two data registers, DACH/L. The DAC output can be
programmed to appear at Pin 3 or Pin 12. It should be noted
that in 12-bit mode, the DAC voltage output will be updated as
soon as the DACL data SFR has been written; therefore, the
DAC data registers should be updated as DACH first, followed
by DACL. The 12-bit DAC data should be written into DACH/L
right-justified such that DACL contains the lower eight bits,
and the lower nibble of DACH contains the upper four bits.
Table XV. DACCON SFR Bit Designations
Bit
Name
Description
7
–––
Reserved for Future Use
6
–––
Reserved for Future Use
5
–––
Reserved for Future Use
4
DACPIN
DAC Output Pin Select.
Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC).
Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1).
3
DAC8
DAC 8-bit Mode Bit.
Set by user to enable 8-bit DAC operation. In this mode, the 8-bits in DACL SFR are routed
to the 8 MSBs of the DAC, and the 4 LSBs of the DAC are set to zero.
Cleared by user to operate the DAC in its normal 12-bit mode of operation.
2
DACRN
DAC Output Range Bit.
Set by user to configure DAC range of 0–AVDD.
Cleared by user to configure DAC range of 0 V–2.5 V (VREF).
1
DACCLR
DAC Clear Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to reset DAC data registers DACL/H to zero.
0
DACEN
DAC Enable Bit.
Set to 1 by user to enable normal DAC operation.
Cleared to 0 by user to power down the DAC.
DACH/L
DAC Data Registers
Function
DAC Data Registers, written by user to update the DAC output.
SFR Address
DACL (DAC Data Low Byte)
FBH
DACH (DAC Data High Byte)
FCH
Power-On Default Value
00H
Both Registers
Bit Addressable
No
Both Registers
Using the D/A Converter
The on-chip D/A converter architecture consists of a resistor
string DAC followed by an output buffer amplifier, the func-
tional equivalent of which is illustrated in Figure 21.
R
ADuC834
AVDD
VREF
OUTPUT
BUFFER
DAC
12
HIGH-Z
DISABLE
(FROM MCU)
Figure 21. Resistor String DAC Functional Equivalent
Features of this architecture include inherent guaranteed mono-
tonicity and excellent differential linearity. As illustrated in
Figure 21, the reference source for the DAC is user selectable in
software. It can be either AVDD or VREF. In 0-to-AVDD mode,
the DAC output transfer function spans from 0 V to the voltage
at the AVDD pin. In 0-to-VREF mode, the DAC output transfer
function spans from 0 V to the internal VREF (2.5 V). The DAC
output buffer amplifier features a true rail-to-rail output stage
implementation. This means that, unloaded, each output is
capable of swinging to within less than 100 mV of both AVDD
and ground. Moreover, the DAC’s linearity specification (when
driving a 10 k
resistive load to ground) is guaranteed through
the full transfer function except codes 0 to 48 in 0-to-VREF
mode and 0 to 100 and 3950 to 4095 in 0-to-VDD mode.
Linearity degradation near ground and VDD is caused by saturation
of the output amplifier, and a general representation of its effects
(neglecting offset and gain error) is illustrated in Figure 22. The
dotted line in Figure 22 indicates the ideal transfer function, and
the solid line represents what the transfer function might look
like with endpoint nonlinearities due to saturation of the output
amplifier.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-ADUC847QSZ | KIT DEV QUICK START FOR ADUC847 |
| GBM24DTKT | CONN EDGECARD 48POS DIP .156 SLD |
| EVAL-ADUC7026QSZ | KIT DEV FOR ADUC7026/7027 |
| GEM36DSXS | CONN EDGECARD 72POS DIP .156 SLD |
| GBM18DSAI | CONN EDGECARD 36POS R/A .156 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADUC836QS | 制造商:Analog Devices 功能描述:MCU 8BIT 8052 CISC 62KB+4KB FLASH 3.6V 48LQFP - Bulk 制造商:Analog Devices 功能描述:KIT- ADUC836 DEV SYSTEM |
| EVAL-ADUC841QS | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| EVAL-ADUC841QSP2 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
| EVAL-ADUC841QSPZ | 功能描述:KIT DEV QUICK START ADUC841 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 通用嵌入式開(kāi)發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:QuickStart™ PLUS 套件 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類(lèi)型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁(yè)面:659 (CN2011-ZH PDF) |
| EVAL-ADUC841QSPZ | 制造商:Analog Devices 功能描述:Silicon Manufacturer:Analog Devices C |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。