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參數(shù)資料
| 型號： | EM6617VVVST11A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, RISC MICROCONTROLLER |
| 封裝： | STICKY TAPE |
| 文件頁數(shù)： | 40/66頁 |
| 文件大?。?/td> | 759K |
| 代理商： | EM6617VVVST11A |
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EM6617-1
EM Microelectronic-Marin SA , 3/99 Rev. B/258
40
Any interrupt request sent by a periphery cell while the corresponding mask is not set will not be stored in the
interrupt request register. All interrupt requests are stored in their
IRQxx
registers depending only on their mask
setting and not on the general interrupt enable status.
Whenever the EM6617-1 goes into HALT Mode the
IntEn
bit is automatically set to 1, thus allowing to resume
from halt mode with an interrupt. This behavior is blocked if SWBAuto is set high. In this case the peripheral
interrupts are disabled until the SWBAuto bit is reset low. Please refer also to the SWB chapter 9.
13.1
Interrupt control registers
Table 13.1.1 register RegIRQ1
Bit
3
2
1
0
W*; Writing of 1 clears the corresponding bit.
Name
IRQPA[3]
IRQPA[2]
IRQPA[1]
IRQPA[0]
Reset
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Port A PA[3] interrupt request
Port A PA[2] interrupt request
Port A PA[1] interrupt request
Port A PA[0] interrupt request
Table 13.1.2 register RegIRQ2
Bit
3
2
1
0
W*; Writing of 1 clears the corresponding bit.
Name
IRQHz1
IRQHz32/8
IRQEEP
IRQADC
Reset
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Prescaler interrupt request
Prescaler interrupt request
EEPROM interrupt request
ADC interrupt request
Table 13.1.3 register RegIRQ3
Bit
3
2
1
0
W*; Writing of 1 clears the corresponding bit.
Name
--
IRQVLD
IRQCount0
IRQCntComp
Reset
R/W
Description
0
0
0
R/W*
R/W*
R/W*
VLD interrupt request
Counter interrupt request
Counter interrupt request
Table 13.1.4 register RegIRQMask1
Bit
3
2
1
0
Interrupt is not stored if the mask bit is 0.
Name
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
MaskIRQPA[3]
MaskIRQPA[2]
MaskIRQPA[1]
MaskIRQPA[0]
Port A PA[3] interrupt mask
Port A PA[2] interrupt mask
Port A PA[1] interrupt mask
Port A PA[0] interrupt mask
Table 13.1.5 register RegIRQMask2
Bit
3
2
1
0
Interrupt is not stored if the mask bit is 0.
Name
Reset
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
MaskIRQHz1
MaskIRQHz32/8
MaskIRQEEP
MaskIRQADC
Prescaler interrupt mask
Prescaler interrupt mask
EEPROM interrupt mask
ADC interrupt mask
Table 13.1.6 register RegIRQMask3
Bit
3
2
1
0
MaskIRQCntComp
Interrupt is not stored if the mask bit is 0
Name
--
Reset
R/W
Description
MaskIRQVLD
MaskIRQCount0
0
0
0
R/W
R/W
R/W
VLD interrupt mask
Counter interrupt mask
Counter interrupt mask
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