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參數(shù)資料
| 型號： | EM6617VVVST11A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.032768 MHz, RISC MICROCONTROLLER |
| 封裝： | STICKY TAPE |
| 文件頁數(shù)： | 33/66頁 |
| 文件大?。?/td> | 759K |
| 代理商： | EM6617VVVST11A |
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EM6617-1
EM Microlectronic-Marin SA , 3/99 Rev. B/258
33
10. 2-Channel ADC (8-bit digital converter)
The EM6617-1 contains one 8-bit ADC with 2 independent input channels. In addition one can choose also Vref
and Vgnd as ADC input. The control logic uses an internal analogue multiplexor to select the channel to be
converted. When data conversion is complete, indicated by a DATA VALID signal, the control logic saves the
converted value in the
RegADCDataH
and the Shadow Low registers.
RegADCDataL
registers is updated
when reading the
RegADCDataH
register. At the end of conversion an interrupt
IRQADC
is sent to the
μ
P. The
architecture of the ADC is illustrated in Figure 25.
The ADC 8 bit contains
an inherent sample and
hold function : the input
voltage is sampled during
acquisition
clock cycles) and is held
until
the
conversion.
conversion time is 10
clock cycles.
phase
(2
end
of
Total
Figure 25. ADC 8 Bit Architecture
External
8-BIT CHARGE
REDISTRIBUTION
ADC CORE
Vgnd
4-Bit Internal Data Bus
RdHigh
IRQ
RdLow
RegADCDataL
RdLow
Shadow Low
RegADCDataH
RdHigh
4
SVref1/2Sel
Start
Convert
Channel
select
Control
Logic
VrefInt
Vref1
Vref2
Vref
Vin
Convert
Data[7 :1]
Data Valid
AIN
BIN
0
3
1
2
8
2
VDD
Vgnd
V
DD
V
SS
IRQADC
Ck[16]
Figure 26. ADC 8 Bit Timing
Start Convert
ADC Clock
1
9
8
7
6
5
4
3
2
10
Data Valid
Re-sampling
8 clocks conversion
Sample&Hold
IRQADC
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