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參數(shù)資料
| 型號(hào)： | EDS1232AABB-75L |
| 英文描述： | SDRAM|4X1MX32|CMOS|BGA|90PIN|PLASTIC |
| 中文描述： | 內(nèi)存| 4X1MX32 |的CMOS | BGA封裝| 90PIN |塑料 |
| 文件頁(yè)數(shù)： | 55/55頁(yè) |
| 文件大?。?/td> | 570K |
| 代理商： | EDS1232AABB-75L |
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EDS1232AABB, EDS1232AATA
Data Sheet E0205E30 (Ver. 3.0)
9
Relationship Between Frequency and Minimum Latency
Parameter
-60
-75
Frequency (MHz)
166
133
100
tCK (ns)
Symbol
6
7.5
10
Notes
Active command to column command
(same bank)
lRCD
3
2
3
2
1
Active command to active command
(same bank)
lRC
10
8
9
7
1
Active command to precharge command
(same bank)
lRAS
7
6
5
1
Precharge command to active command
(same bank)
lRP
3
2
3
2
1
Write recovery or data-in to precharge
command (same bank)
lDPL
2
1
Active command to active command
(different bank)
lRRD
2
1
Self refresh exit time
lSREX
1
2
Last data in to active command
(Auto precharge, same bank)
lDAL
5
4
5
4
= [lDPL + lRP]
Self refresh exit to command input
lSEC
10
8
9
7
= [lRC]
3
Precharge command to high impedance
(CL = 2)
lHZP
2
2
(CL = 3)
lHZP
3
Last data out to active command
(auto precharge) (same bank)
lAPR
1
Last data out to precharge
(early precharge)
(CL = 2)
lEP
–1
–1
(CL = 3)
lEP
–2
Column command to column command
lCCD
1
Write command to data in latency
lWCD
0
DQM to data in
lDID
0
DQM to data out
lDOD
2
CKE to CLK disable
lCLE
1
Register set to active command
lMRD
2
/CS to command disable
lCDD
0
Power down exit to command input
lPEC
1
Notes: 1. IRCD to IRRD are recommended value.
2. Be valid [DESL] or [NOP] at next command of self refresh exit.
3. Except [DESL] and [NOP]
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| EDS1232AABB-75L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM |
| EDS1232AASE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-60-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-60L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-75-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
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