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參數(shù)資料
| 型號(hào)： | EDS1232AABB-75L |
| 英文描述： | SDRAM|4X1MX32|CMOS|BGA|90PIN|PLASTIC |
| 中文描述： | 內(nèi)存| 4X1MX32 |的CMOS | BGA封裝| 90PIN |塑料 |
| 文件頁(yè)數(shù)： | 20/55頁(yè) |
| 文件大?。?/td> | 570K |
| 代理商： | EDS1232AABB-75L |
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EDS1232AABB, EDS1232AATA
Data Sheet E0205E30 (Ver. 3.0)
27
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 s after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, /CS DQM and DQ pins. If these pins go high before power up,
the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 s or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. We recommend that by keeping DQM and CKE to High, the
output buffer becomes High-Z during Initialization sequence, to avoid DQ bus contention on memory system formed
with a number of device.
VDD, VDDQ
Power up sequence
Initialization sequence
100
s
0 V
Low
CKE, DQM
CLK
/CS, DQ
200
s
Power stabilize
Power-up sequence and Initialization sequence
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| EDS1232AABB-75L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM |
| EDS1232AASE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-60-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-60L-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
| EDS1232AASE-75-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M bits SDRAM (4M words x 32 bits) |
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